This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Reduce clock frequency and timing measurement

Other Parts Discussed in Thread: OMAP-L137

Hi all

I'm working with the OMAP-L137 EVM and only use the C6747. For evaluation purpose I need to reduce the clock frequency and measure the time that my algorithm needs. Now first question: How can I reduce the clock frequency for the C6747? All I've done is I've changed "DSP speed in MHz (CLKOUT)" in the DSP/BIOS config tool. But I'm not really sure if the change I've made had any effect because the execution times I've measured were quasi the same for 300 MHz, 200 MHz or even 10 MHz. I've measured both in software using CLK_getltime() * CLK_getprd() / CLK_countspms() and by looking at SPI signals on the scope since SPI is only active after the algo completes.

Could you please tell me if there are any problems with clock frequency reduction like I do it or with the time measurement in software? Anyway, the time measurements on the scope and in software correlate well enough, so I think it's either a problem in clock frequency reduction or my algorithm performs well (but this would be strange).;)

Last question: does reducing the DSP clock frequency have an influence on SPI?

Thanks for all your help

Andreas

 

  • You can check if your frequency settings took effect or not by examining the PLLC registers (base address 0x01C1 1000h). The PLL multiplier and divider registers must change in order for the DSP clock frequency to change. See the System Reference Guide for your device for more information.

    The easiest way to change the frequency for evaluation purposes would be through the GEL file. Modify the PLLM and POSTDIV values in the SETUP_PLL() function and run it to modify the DSP frequency.

    The SPI clock is sourced from SYSCLK2, which is fixed to half the DSP clock. So reducing the DSP clock will also reduce the SPI clock proportionally.

    Jeff

  • Andreas,

    You can see the PLL and peripheral clock information that Jeff mentioned in the System Reference Guide.

    TIMERs 0 and 1 are both clocked by the OSCIN reference frequency so they should be running at the same speed regardless of the DSP frequency.

    -Tommy

  • Jeff and Tommy,

    Thank you for your answers. I worked!:)

    Best regards,

    Andreas