Hi Support,
my customer is facing issues when trying to use SPI3, SPI4 on AM5728 rev2.0 EVM board.
Current goal is to have master SPI3 for Tx only, slave SPI4 for Rx only, both pinmuxed to P16 connector.
Please see relevant excerpts...
- ... from boardPadDelayInit.c : boardPadDelayCfg_t pad[]:
/* SPI4 slave, Tx on D1; Rx unused */
/* SPI3 - clk on B12 (P16-GPIO5_10: 34) */
{0x16D4, 0xD0003, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},
/* SPI3 - d1 on A11 (P16-GPIO5_11: 4); MOSI Tx */
{0x16D8, 0xD0003, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},
/* SPI3 - d0 on B13 (P16-GPIO5_12: 33); MISO (UNUSED) */
{0x16DC, 0xD0003, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},
/* SPI3 - cs0 on A12 (P16-GPIO5_17: 3) */
{0x16E0, 0x90003, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},
/* SPI4 slave, Rx on D0; Tx unused */
/* SPI4 - clk on N7 (P16-VIN3A_HSYNC: 9) */
{0x1460, 0xD0008, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},
/* SPI4 - d1 on R4 (P16-VIN3A_VSYNC: 37); MISO (UNUSED)*/
{0x1464, 0x90008, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},
/* SPI4 - d0 on N9 (P16-VIN3A_DE0: 14); yellow; MOSI (Rx-input) */
{0x1468, 0xD0008, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},
/* SPI4 - cs0 on P9 (P16-VIN3A_FLD: 44)*/
{0x146C, 0xD0008, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},
- ... from evmAM572x_clock.c: Board_moduleClockInit():
/* Added SPI3 support for master loopback */
CSL_FINST(l4PerCmReg->CM_L4PER_MCSPI3_CLKCTRL_REG,
L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI3_CLKCTRL_REG_MODULEMODE, ENABLE);
/* Added SPI4 support for slave loopback */
CSL_FINST(l4PerCmReg->CM_L4PER_MCSPI4_CLKCTRL_REG,
L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI4_CLKCTRL_REG_MODULEMODE, ENABLE);
- ... from main_mcspi_slave_mode.c: SPI_test_mst_slv_xfer():
#define MCSPI3_BASE 0x480b8000
#define MCSPI4_BASE 0x480ba000
#define WR_REG(reg, val) (*(uint32_t*)(reg) = val)
#define RD_REG(reg, var) (var = *(volatile uint32_t*)reg)
#define SPI3_CH1CONF (MCSPI3_BASE + 0x12c)
#define SPI4_CH1CONF (MCSPI4_BASE + 0x12c)
if (master == true)
{
transaction.txBuf = (Ptr)masterTxBuffer;
transaction.rxBuf = (Ptr)addrMasterRxBuf;
/* Set master D0_in D1_out */
RD_REG(SPI4_CH1CONF, cnf);
cnf |= 1 << 16;
cnf &= ~((1 << 18)|(1 << 17));
WR_REG(SPI4_CH1CONF, cnf);
}
else
{
transaction.txBuf = (Ptr)slaveTxBuffer;
transaction.rxBuf = (Ptr)addrSlaveRxBuf;
/* Set slave D0_in D1_out */
RD_REG(SPI3_CH1CONF, cnf);
cnf |= 1 << 16;
cnf &= ~((1 << 18)|(1 << 17));
WR_REG(SPI3_CH1CONF, cnf);
}
---------------
Then they pairwise interconnect pins on P16, so that SPI3 master can transmit to SPI4 slave receiver:
34-9 (clk)
4-14 (data)
3-44 (cs0)
... and they then continue in stepping through main_mcspi_slave_mode.c:
/* Initiate SPI transfer */
transferOK = SPI_transfer(spi, &transaction);
if(transferOK) {
/* ... */
}
they don't receive any message neither in masterRxBuffer, nor in slaveRxBuffer, although by looking at oscilloscope, master SPI is transmitting.
- Another finding was that, when swapping the master-slave roles so that SPI3 is slave, SPI4 is master, then SPI3 slave receives the message correctly, SPI4 master receives nothing.
- Yet another finding is when trying SYSTEM_TEST, setting clock high on SPI4 and reading on SPI3 register, 1 is detected, as expected, but when setting clock on SPI3 and reading on SPI4, 0 is detected.
(This seems to me like if the SPI4 clock input is not working properly for unknown reason. Or I could also miss something in the device configuration?)
Could you please give me some hints?
Thank you in advance,
regards,
Alberto
