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Configuration of dm647 CLK module

Geoff
Prodigy 195 points

We are using DSPBIOS on a TMS320C647. Our crystal is 40 mhz, giving (we believe) an internal clock of 800 mhz. We have the following in the text configuration file:

:

bios.GBL.CLKIN = 40000;
bios.GBL.CLKOUT = 800.0000;
bios.CLK.SPECIFYRATE = 1;
bios.CLK.TIMERSELECT = "Timer 0";
bios.CLK.HIRESTIME = true;
bios.CLK.MICROSECONDS = 1000.0;
bios.CLK.CONFIGURETIMER = false;

:

however, reading timer0 registers we see:

EMUMGT_CLKSPD : 0x00060001

CNTLO : 0x00006037

CNTHI : 0x00000000

PRDLO : 0x000208D5 (133333)

PRDHI : 0x00000000

TCR : 0x00000090

TGCR : 0x00000007

 

We expected to see the period register loaded with 800,000 however it is loaded with 133,333. This happens to be 800,000 divided by 6 and I see that the CLKDIV part of the  EMUMGT_CLKSPD register is set to 6.

Someone please explain the BIOS initialization of the timer0 and how to get the low res counter to count in milliseconds.

 

Thanks

Geoff

  • 0
    TI__Guru*** 125430 points

    Please see Table 6-5 "Clock Domain Assignment" in the data sheet.  It mentions that all peripherals (e.g. the Timers) are clocked at CPU/6.  That's why the PRD register is loaded with 133,333.

    FYI, BIOS does not actually do the PLL configuration so make sure that either a gel file or your bootloader code is configuring the PLL to the expected 800 MHz.  Otherwise the Timer won't be running at the anticipated 133.33 MHz.