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66AK2G02: Reliability warning in DDR3 Design Requirements

Debora
Intellectual 645 points

Part Number: 66AK2G02

SPRABI1B, the DDR3 Design Requirements for Keystone Devices, has a dire warning about the reset to the DDR3 controller:

CAUTION—The TI DSP DDR3 controller cannot be held in reset for more than
one hour during the initial power-up. Also, the TI DSP DDR3 controller
cannot be held in reset for more than 5% of its total power-on hours. Exceeding
these limits will cause a gradual reduction in the reliability of the part.

Does this mean that the 66AK2G02 must not be held in reset for more than very brief times?  In previous designs we have held our SoC in reset to tristate its outputs while externally programming flashes on the board.

  • 0
    TI__Guru**** 161600 points
    Hi,

    I've notified the design team to help on this. Their feedback will be posted here.

    Best Regards,
    Yordan
  • 0
    TI__Mastermind 42545 points
    Hi Debora,
    Holding the board is reset while programming the on board flash components shouldn't be a problem. I doubt that will exceed the 1 hour limit. Note that holding the part in reset for an hour will not cause it to fail. The part will age over time if power is applied and the leveling of the DDR3 becomes less accurate as the part ages. During normal operation, this aging will have no effect on the operation of the DDR over the life of the part but holding the part in reset will speed that process.
    The warning was added because we have had customers put the part into a reset state when it was not actively in use. That would result in a situation where the part was in reset for long periods of time during normal operation and only released from reset when the device was needed. The part is designed to be removed from reset after the power has been applied. Software can be used to place it into an idle state but holding it in reset is not a valid usecase.
    Regards,
    Bill