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GPMC burst writes

John Stephens
Prodigy 75 points

I am trying to do an 8-word burst write to a generic SRAM-type interface from the OMAP35x GPMC, but cannot tell from Figure 11-21 in the SPRUF98 how to use nBE[1:0] to get the data.  Can someone shed some light on this or point me to a document that describes this in more detail.  Thanks

John

  • 0
    TI__Genius 9190 points

    Hello John,

    the nBE0 and nBE1 signals are used to tell you if the byte is being written to the memory.  nBE0 goes low if the lower byte is being written and nBE1 goes low when byte 1 is being written. 

    Here is a good link on configuring the GPMC for the OMAP35x device...this link does not talk about nBE, but I thought it might help you for configuring your system. 

    http://processors.wiki.ti.com/index.php/Tips_for_configuring_OMAP35x_GPMC_registers

    Best regards,
    Jeff

  • 0 in reply to Jeff Culverhouse
    Prodigy 75 points

    Jeff-

    Thanks for your responsiveness.  Perhaps I didn't explain well enough.  I would like to receive a burst of 8 16-bit words into my FPGA using the multiplexed address/data mode.  In order to do so, I need to increment an address pointer for each new data word, but it is unclear how the nBE signals change for this type of transaction.  Do they toggle for 16-bit writes?  If so, do they simply binary count from 00 to 11 (twice through for an 8 word burst)?  I cannot simply increment the pointer at each successive clock since Figure 11-21 shows D0 being present on the bus for several clocks, D1-D6 are present for one GPMC_CLK each, and D7 is present for two GPMC_CLKs. Hope that clarifies my question.  Thanks again for your help.

    John

  • 0 in reply to John Stephens
    TI__Genius 9190 points

    Hello John,

    I didn't figure it was that easy, but I thought I would give it a shot :)

    For 16b writes nBE0 and nBE1 do not toggle, so nBE is not a good signal to use for this.  I would try using WE.  I have attached a capture of the GPMC setup in 16b mode with the ARM writing multiple words.

    Best regards,
    Jeff

  • 0 in reply to Jeff Culverhouse
    Prodigy 75 points

    Jeff-

    Thanks for the picture. That was really helpful. Can you answer another question for me on the GPMC? It seems that we're trying to do a single read from a register in our target device, but the reads always come back as a 32 word burst read. Any thoughts on what may cause that? You can read more detail on the problem from my coworker here:

    http://e2e.ti.com/support/dsp/omap_applications_processors/f/447.aspx

     

    Thanks again.

    Regards,

    John

    P.S. Sorry for the long time in repsonding. Our project was turned off for a while and then recently turned back on. 

  • 0 in reply to John Stephens
    Prodigy 160 points

    I met the problem just opposite to yours.sinceI do the single read and write well.but I met a problem when I do the sync burst read:

    I export the function gpmc_cs_set_timings ,and add some code like below to do the sync burst read:

    l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
    l=l|GPMC_CONFIG1_READTYPE_SYNC;
    l=l|GPMC_CONFIG1_READMULTIPLE_SUPP;
    l=l|GPMC_CONFIG1_CLKACTIVATIONTIME(1);
    gpmc_cs_write_reg(cs, GPMC_CS_CONFIG6, 0x0);

    I call this function in my driver code,print the register,the result is look like below,I only want to do sync burst read,but I can't read anything on the D[0]-D[15] lines

    I am looking forward to your reply.please help me,if you can give me some source code about sync burst read,It would be better for me to understand.Thanks again.

    GPMC_CS_CONFIG1=62001001
    GPMC_CS_CONFIG2=001c0b00
    GPMC_CS_CONFIG3=00010900
    GPMC_CS_CONFIG4=16090b00
    GPMC_CS_CONFIG5=02091e0b
    GPMC_CS_CONFIG6=00000000
    GPMC_CS_CONFIG7=00000f6c