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DM365 DVEVM : CPLD link wire transplant

NickAllen
Intellectual 525 points

Hi all,

Before we get PCB's manufactured I want to ensure our schematic is correct (so that if we have any issues, we can be fairly confident that it is PCB stackup and/or physical routing related). I have subsequently removed various MUX's as well as the CPLD from the DVEVM and begun to hard wire tracks manually. This will also allow us to start modifying linux drivers in preparation for when our PCBs arrive.

Unlike the Ethernet & Video MUXs however, the CPLD however is a rather complex bugger - particularly when it comes to the power & PRTC sub systems because of its criticality (and my current lack of complete understanding). I have not powered up the board since removing the CPLD as I am concerned about the power sequencing as well as being uncertain as to why some of the IO are routed into the CPLD as they are. I have downloaded the CPLD firmware .zip from Spectrum Digital & wish to try investigate in a bit more detail what it is doing. Can anyone recommend what I can use to open these files (freeware)? I do not want to reprogram the CPLD, merely see what it is currently doing to better get our boards up and running without it.

Sincerely,
NickA

  • 0
    TI__Mastermind 41665 points

    NickAllen said:
    Can anyone recommend what I can use to open these files (freeware)?

    If you are familiar with VHDL you can open the .vhd file in any text editor to see what the logic is inside the CPLD, this is how I usually analyze them, but I only look at very basic pieces usually (tracing a particular signal for example).

    Though I have not used any VHDL tools in a long time, you might consider looking at the Altera tools since this is an Altera CPLD being used, the Quartus II development tool appears to have a 30 day trial (not quite freeware, but maybe good enough for your needs), though I have not used it, I suspect it is what would open the CPLD project files included in that zip.

    EDIT: I just wanted to add that running small gauge wire all over the EVM runs a great deal of cross talk risk, particularly if you try to do this for any of the higher speed interfaces, so doing this might cause more headaches than it would resolve by just debugging your newly printed PCBs. I guess it does not hurt anything if you have an EVM to spare, but in my experience replacing something like the CPLD on the EVM with little surface mount soldered wires is like trying to build a bicycle out of toothpicks, it is possible but it has to go very slow, will be tedious to put together and likely to break easily.

  • 0
    TI__Expert 5955 points

    Hi Nick,

    If you are looking at the VHDL code for U33 under \boards\evmdm365_v1\firmware\CPLD\DM365_u33_xxxxxxx directory, you will see the DM365_U33.vhd file. You can use almost any editor (TEXTPAD, WORDPAD,..) to open it.

    Hope this helps.

    Thanks,

    Tai

  • 0 in reply to Bernie Thompson TI
    Intellectual 525 points

    Hi Bernie,

    Thanks for the wisdom :) I do have three EVMs spare so I am willing to take the risk. I am primarily interested in the power sequencing, reset control as well as NAND so there shouldnt be too many toothpicks!

    Sincerely,
    NickA