OMAP35x ISP CCDC Raw Cmos Sensor Data

Armen,

What is the purpose for using the CBUFF logic? You can get the same result by managing your own circular buffer (see end of this posting) with little complexity.  Without having looked at the register settings above, here are some answers/suggestions for your questions:

Question 1:  

What is the difference in the address pointers given to the CCDC_SDR_ADDR register and the CBUFF0_START register? I am writing the same pointer to both registers.

Answer 1: CCDC_SDR_ADDR is the start address where the captured frame data will be written into physical memory.

From the TRM: The CBUFFx_START and CBUFFx_END register define the virtual address range managed by the circular buffer. It usually corresponds to the address region where one image frame is written by the camera ISP.

Question 2:

I am always getting an  IRQ_CBUFF0_INVALID in the CBUFF_IRQSTATUS (IRQ_CBUFF0_INVALID[1]=0x1) register. What could be the cuase of this status error?

Answer 2:  See TRM table 12.18 for different conditions. In a nutshell:"This event indicates a wrong configuration of the circular buffer, the camera ISP, or bogus software".

Question 3:

When I interogate the memory that the ISP is writing to, I always see a data being written. I was hoping that the data does not get written to the memory until I write a 0x1 to  CBUFF0_CTRL. DONE[2] bit. This way I can make sure the data being processed by the CPU is not being changed by the ISP CCDC module.

Answer 3: This is probably because the CCDC is not in one-shot mode, so it continues to write data in the buffer provided by CCDC_SDR_ADDR. It looks like what you are trying to accomplish could be done easily by managing your own circular buffer as follows:

0. Setup a buffer that can contain n frames: sizeof n * buffer size, starting on 32 byte boundary (condition for CCDC_SDR_ADD)

1. Set the CCDC in one-shot mode. This will capture one frame and then suspend the CCDC.

2. Wait for the frame capture completion -  VDx interrupt from the CCDC (see TRM 12.5.4.3)

3. check the read vs write buffer pointers or the number of frames captured sofar (looks from your narritive above you want to capture only 2 frames)

4. If they are close, do not re-enable the CCDC (i.e. drop the next frame)

5. if they are not close, re-enable the CCDC with the new write address, making sure that you wrap the write address when you have done n frames. You can do all this in the Vertical Sync interval, using the VDx interrupt from the CCDC, latching in the first edge. This is plenty of time to setup the CCDC output and re-enable.

Hi Tiemen,

Thanks for your responses.

1. I tried to use the One Shot mode as you suggested by Setting up the Preview engine to take the Raw Data from the CCDC_SDR_ADDR location. I set the PRV_PCR.ONESHOT[3]=1,PRV_PCR.SOURCE[2]=1 and PRV_PCR.ENABLE[0]=1.  Same with the Resizer Set the RSZ_PCR.ONESHOT[2]=1 and RSZ_PCR.ENABLE[0]=1.

The system hangs up. with BUSY on all 3 registers being high. CCDC_PCR.BUSY[1]=1,PRV_PCR.BUSY[1] and RSZ_PCR.BUSY[1]=1. They never go to 0.

2. I am still confused on the CBUFFx_START register. The Camera document from Ti gives this formula:

The formula used from TI Document:

Literature Number: SPRUFA2A
September 2008

ADDR = CBUFFx_STATUS [3:0] CPUW x CBUFFx_WINDOWSIZE + CBUFFx_START  1.5.8.6 Operations and

1.5.8.3 Register Setup

All registers of the circular buffer to be used (CBUFFx, x=0 or 1) have to be initialized for correct
operation.
The CBUFFx_START and CBUFFx_END register define the virtual address range managed by the
circular buffer. It usually corresponds to the address region where one image frame is written by the
camera ISP.

Should I be programming the CBUFFx_START with the virtual address of the Physical address space?

Thanks

Armen.

Armen,

On (1) just to make sure, the sequence in which you enable/disable the individual modules should always be in order of their position in the processing chain, where you ENABLE working from the back of the chain (module is ready for data input BEFORE the data stream starts) and DISABLE working from the front of the chain (cut off data in first, let the other modules finish processing the data before you disable them). SInce the chain you use is Camera -> CCDC -> PRV -> RSZ, the sequence that needs to be followed is:

Enable:  Enable RSZ, Enable PRV, enable CCDC, enable Camera

Disable:  Disable Camera, Wait for busy "done" then disable CCDC, Wait for busy "done" then disable PRV, Wait for busy "done" then disable RSZ.

If you do not follow this sequence, the CCDC for example will be putting out data to the PRV, but it has not started yet, so once it starts, it will be busy waiting for data which will never complete the frame, etc.

I will check on (2)

Hi Tiemen,

Followed your suggestion with CCDC and PRV only no RSZ for now. Enabled: PRV_PCR = 0x10000D(PRV in oneshot and source is memory) and CCDC_PCR =0x1. If I have the CCDC_FMTCFG.VPEN[15] = 1 the CCDC_PCR.BUSY[1]=1 all the time. If I have CCDC_FMTCFG.VPEN[15]=0 the CCDC_PCR.BUSY[1] = transitions from 1 to 0. In this case I disabled the Camera and check the PRV_PCR.BUSY[1] bit which was equal to 1 (busy) all the time.  Also tried to disable the camera before reading the CDC_PCR.BUSY[1] bit . Had the same results.  One caveat is that I am not sure when to turn off the camera if I have to turn it off before the CCDC. I have tried before and after reading the CCDC_PCR register.  I am using the CCDC_PCR.BUSY[1] going to 0 as a Done indicator before I turn off the camera.

In Summary the busy bit goes off if CCDC_FMTCFG.VPEN[15] =0 and stays high if CCDC_FMTCFG.VPEN[15] =1. Any Suggestions?

Thanks

Armen.

Armen,

I think the easiest way is to start from the beginning and do one step at the time, testing each step before moving on to the next.

The first thing to do is to setup your registers on the CCDC according to TRM tables 12-69 and 12-70 default to using the IPIPE between the different modules (don't capture to memory yet). Once you have done that, enable the CCDC and then the camera and see if you get any data into the CCDC (check to see if you can get any VD0/VD1 interrupts). Leave the PRV and RSZ enabled and do not worry about them yet.  Leave the camera and the CCDC in ENABLED mode, first try to get your VSYNC frame/field capture interrupts working.

Once you are able to get these interrupts (meaning the CCDC completed the capture), we can go to one-shot mode next. Once you see that the one-shot is completed, we will go and setup the output to memory, etc.

Let me know when you have completed step 1 - capture the CCDC data and actually see the frame completion interrupts. From that point on we can talk about changing one register set at the time for each consecutive step in the process.

Regards
Tiemen

Hi Tiemen,

I did what you asked and built up from simple to memory write enables in one-shot mode. I think the CCDC and Preview engines are working in One-Shot mode. I am having issues with the Re-Sizer Engine. See the 3 different configurations and results below.

Below are 3 scenarios that I tried. Scenario 1, I had Re-sizer engine input source from preview engine. Scenarios 2 and 3 the Re-sizer engine had it's input set to Pre-View memory space. As you can see below I got overflow interrupts for scenarios 2 and 3 on the Re-Sizer engine. there was some data that was being written to the re-sizer memory space; but, it did not make sense. In Scenario 1 Re-sizer did not write to memory, nor did I get any overflow or any indications that the Re-Sizer was doing anything.

1. I have the following interrupts occurring after enabling the following registers: RSZ_SDR_INADD = 0x0, RSZ_CNT =0x0003FCFF, RSZ_PCR = 0x5, PRV_PCR = 0x18000D and CCDC_PCR =0x1

ISP_IRQ0STATUS = 80100300 meaning  CCDC_VD0_IRQ[8] = 1, CCDC_VD1_IRQ[9]= 1, PRV_DONE_IRQ[20]= 1,  HS_VS_IRQ[31]=1 and I see Cmos data in the CCDC memory space and Preview in Preview memory space.The Resizer memory space is not written. (NO ACTIVITY ON RESIZER)

2. I have the following interrupts occurring after enabling the following registers: RSZ_SDR_INADD = buffer_3_pntr, RSZ_CNT =0x1003FCFF, RSZ_PCR = 0x5, PRV_PCR = 0x18000D and CCDC_PCR =0x1

ISP_IRQ0STATUS = 82100300 meaning  CCDC_VD0_IRQ[8] = 1, CCDC_VD1_IRQ[9]= 1, PRV_DONE_IRQ[20]= 1, OVF_IRQ[25] =1, HS_VS_IRQ[31]=1 and I see Cmos data in the CCDC memory space and Preview in Preview memory space.The Resizer memory space gets updated with a repeating 0x80, 0x00, 0x80, 0x00.... and if I look into SBL_PCR register I see CCDCPRV_2_RSZ_OVF[24]= 1. ( ACTIVITY ON RE-SIZER BUT FAULTY)

3. I have the following interrupts occurring after enabling the following registers: RSZ_SDR_INADD = buffer_3_pntr, RSZ_CNT =0x1003FCFF, RSZ_PCR = 0x5, PRV_PCR = 0x10000D and CCDC_PCR =0x1

 ISP_IRQ0STATUS = 82100300 meaning  CCDC_VD0_IRQ[8] = 1, CCDC_VD1_IRQ[9]= 1, PRV_DONE_IRQ[20]= 1, OVF_IRQ[25] =1, HS_VS_IRQ[31]=1 and I see Cmos data in the CCDC memory space and Preview in Preview memory space.The Resizer memory space gets updated with a repeating 0x80, 0x00, 0x80, 0x00.... and if I look into SBL_PCR register I see CCDCPRV_2_RSZ_OVF[24]= 1.( ACTIVITY ON RE-SIZER BUT FAULTY)

P.S  I don't see any Re-sizer  done happening.

Thanks

Armen

Armen,

1) This indicates that you have gotten a completion interrupt from the resizer, so you have captured the frame, which is good. You need to make sure in your VD0 or VD1 ISR to swap the input and output buffers to the "pong" buffer (ping-pong scheme with 2 buffers) otherwise you will certainly get the overflow condition you see in scenarios 2 and 3. So it looks like you are correctly setup on the CCDC and the PRV. It looks like your CCDC/PRV combination is working correctly, make sure you have a VD0 or VD1 ISR to ping/pong the CCDC out and PRV input buffers. You also need to allocate 2 buffers to get proper flow between the PRV and the RSZ (ping pong that one too).

So now that we have narrowed it to the RSZ setup, please make check the following:

RSZ_PCR - make sure that bit 0 = 1 after every  completion (in memory to memory the RSZ always operates in one-shot mode). Monitor the PCR.BUSY bit to see if it ever goes to 1

RSZ_IN_START: make sure VERT_STRT = 0 for memory based operations.

RSZ_SDR_INADDR must point to the appropriate PRV output buffer you are working on

RSZ_SDR_OUTADDR must point to the capture buffer at the output of the RSZ (Typically the frame buffer for your DSS)

With the above you should see the RSZ_PCR.BUSY go to 1 and the PCR bit 0 go to 0 after a frame cycle. This indicates that the RSZ did indeed start working, Once BUSY is 0, the RSZ operation is completed.

The proper overall sequence with everything in one-shot is:

CCDC setup, PRV setup, RSZ setup - enable RSZ, enable PRV, enable CCDC, enable Camera - wait for VD0/VD1. In the ISR, wait for PRV complete, wait for RSZ complete, switch buffers, enable RSZ, enable PRV, enable CCDC, exit ISR. This should work without a problem as it does in other implementations.

Hi Tieman,

I checked the RSZ_IN_START.VERT_STRT =0.

RSZ_SDR_INADDR  points to the PRV out address.

RSZ_SDR_OUTADDR is pointer is pointing to the output of the re-sizer memory location.

Note: I have 3 memory pointers. mem_p0, mem_p1, mem_p2. and they are used up as follows: CCDC->mem_p0,  mem_p0->PRV->mem_p1, mem_p1->RSZ->mem_p2. The way I understand it, I need to ping-pong like this: CCDC->mem_p0b,  mem_p0a->PRV->mem_p1b, mem_p1a->RSZ->mem_p2 after VDD0/1 ISR, CCDC->mem_p0a,  mem_p0b->PRV->mem_p1a, mem_p1b->RSZ->mem_p2

I think I am following the sequence  you specified. I enabled the RSZ_PCR=0x1, Enable the PRV_PCR = 0x10000D, enable CCDC_PCR =0x1, enable the Camera. I wait for VD0/VD1 and I see it. wait for PRV complete and I do see the it (PRV_PCR.ONESHOT =0 and PRV_PCR.ENABLE=0 and PRV_PCR.BUSY=0), I wait for RSZ_PCR.BUSY=1 and I see it BUSY but it never goes low (always stays high busy). Also  RSZ_PCR.ENABLE =1 . As you mentioned I should not switch ping-pong buffers while the RSZ_PCR.BUSY = 1.

Note: I never saw a RSZ_DONE_IRQ.  Could it be that I may need to program any filter coefficients or I need a certain minimum Horizontal and Vertical pixel size for the resizer to complete?

Thanks

Armen.

Armen,
Believe it or not, the above is good news !! The fact that your RSZ busy bit goes to 1 means that it is processing the input. The fact that it never goes back to 0 means it never gets done. There are a very limited number of reasons why it would do this, the most common one is that there is not enough data in the input buffer to process the frame as you have defined it in the RSZ INSIZE (and to an extend OUTSIZE) registers.

So, check the RSZ registers (provide a dump if you want to) and check to make sure that your data size setup is less or equal to the amount of data in the input buffer. Also make sure that you have not set up any other registers in the RSZ that could make it not complete.

One more quick test I would like you to run to make sure you have data integrity now that your data is flowing through the CCDC and the PRV properly. Take the output data from the PRV and use it to drive the DSS and check that the image on the LCD screen is the undistorted image from the camera.

Regards

Tiemen

Hi Tiemen,

Here is a dump of the ISP, TCTRL, CCDS, PRV and RSZ registers after the vd0/vd1 interrupt.

CCDC:

480bc604 00000000

480bc608 00030400

480bc60c 00000000

480bc610 00000000

480bc614 00000100

480bc618 00000000

480bc61c 00000000

480bc620 ffff00ff

480bc624 00000000

480bc628 00000000

480bc62c 84fe6000

480bc630 00000010

480bc634 00000000

480bc638 00000000

480bc63c 00000000

480bc640 00000000

480bc644 00000000

480bc648 00030003

480bc64c 00000004

480bc650 00000000

480bc654 00008000

480bc658 0000c000

480bc65c 00000200

480bc660 00000200

480bc664 00000000

480bc668 00000000

480bc66c 00000000

480bc670 00000000

480bc674 00000000

480bc678 00000000

480bc67c 00000000

480bc680 00000000

480bc684 00000000

480bc688 00000000

480bc68c 00000000

480bc690 00000000

480bc694 03fe2000

480bc698 00006600

480bc69c 00000000

480bc6a0 00000000

480bc6a4 00000000

PRV

480bce00 0002fe00

480bce04 00100000

480bce08 000001ff

480bce0c 00000200

480bce10 869d4000

480bce14 00000000

480bce18 00000000

480bce1c 00000000

480bce20 8641a000

480bce24 00000000

480bce28 00000015

480bce2c 00000300

480bce30 00000000

480bce34 00000100

480bce38 20202020

480bce3c ee44ee44

480bce40 00000000

480bce44 00000000

480bce48 01000100

480bce4c 01000100

480bce50 01000100

480bce54 01000100

480bce58 00000100

480bce5c 00000000

480bce60 00000000

480bce64 01c2604c

480bce68 080eb3d4

480bce6c 3ec2039e

480bce70 00000000

480bce74 00001000

480bce78 00000000

480bce7c ff00ff00

480bce80 00000000

480bce84 000000e9

480bce88 00000000

480bce8c 00000000

480bce90 00000000

480bce94 00000000

480bce98 00000000

480bce9c 00000000

RSZ

480bd000 0010fe00

480bd004 00000003

480bd008 1003fcff

480bd00c 02000200

480bd010 00000000

480bd014 02000200

480bd018 86cb0000

480bd01c 00000000

480bd020 866f7000

480bd024 00000000

480bd028 00000000

480bd02c 00000000

480bd030 00000000

480bd034 00000000

480bd038 00000000

480bd03c 00000000

480bd040 00000000

480bd044 00000000

480bd048 00000000

480bd04c 00000000

480bd050 00000000

480bd054 00000000

480bd058 00000000

480bd05c 00000000

480bd060 00000000

480bd064 00000000

480bd068 00000000

480bd06c 00000000

480bd070 00000000

480bd074 00000000

480bd078 00000000

480bd07c 00000000

480bd080 00000000

480bd084 00000000

480bd088 00000000

480bd08c 00000000

480bd090 00000000

480bd094 00000000

480bd098 00000000

480bd09c 00000000

480bd0a0 00000000

ISP/ TCTRL

480bc004 00001000

480bc008 00000001

480bc00c 00000000

480bc010 82100300

480bc014 00000000

480bc018 82100300

480bc01c 00000000

480bc020 00000000

480bc024 00000000

480bc028 00000000

480bc02c 00000000

480bc030 00000000

480bc034 00000000

480bc038 00000000

480bc03c 00000000

480bc040 203ff300

480bc044 00000000

480bc048 00000000

480bc04c 00000000

480bc050 d8801084

480bc054 00000000

480bc058 00000000

480bc05c 00000000

480bc060 00000000

480bc064 00000000

480bc068 00000000

480bc06c 00000000

Thanks

Armen

Second dump of registers:

ccdc
480bc600 0001fe01
480bc604 00000001
480bc608 00030400
480bc60c 00000000
480bc610 00000000
480bc614 000001ff
480bc618 00000000
480bc61c 000001ff
480bc620 ffff00ff
480bc624 00000000
480bc628 00000000
480bc62c 84fd0000
480bc630 00000010
480bc634 00000000
480bc638 00000000
480bc63c 00000000
480bc640 00000000
480bc644 00000000
480bc648 00030003
480bc64c 00000004
480bc650 00000000
480bc654 00008000
480bc658 0000c000
480bc65c 00000200
480bc660 00000200
480bc664 00000000
480bc668 00000000
480bc66c 00000000
480bc670 00000000
480bc674 00000000
480bc678 00000000
480bc67c 00000000
480bc680 00000000
480bc684 00000000
480bc688 00000000
480bc68c 00000000
480bc690 00000000
480bc694 03fe2000
480bc698 00006600
480bc69c 00000000
480bc6a0 00000000

PRV
480bce00 0002fe00
480bce04 00100000
480bce08 000001ff
480bce0c 00000200
480bce10 85866000
480bce14 00000000
480bce18 00000000
480bce1c 00000000
480bce20 852ad000
480bce24 00000000
480bce28 00000015
480bce2c 00000300
480bce30 00000000
480bce34 00000100
480bce38 20202020
480bce3c ee44ee44
480bce40 00000000
480bce44 00000000
480bce48 01000100
480bce4c 01000100
480bce50 01000100
480bce54 01000100
480bce58 00000100
480bce5c 00000000
480bce60 00000000
480bce64 01c2604c
480bce68 080eb3d4
480bce6c 3ec2039e
480bce70 00000000
480bce74 00001000
480bce78 00000000
480bce7c ff00ff00
480bce80 00000000
480bce84 000000e9
480bce88 00000000
480bce8c 00000000
480bce90 00000000
480bce94 00000000
480bce98 00000000
480bce9c 00000000
480bcea0 00000000

RSZ
480bd000 0010fe00
480bd004 00000003
480bd008 1003fcff
480bd00c 02000200
480bd010 00000000
480bd014 02000200
480bd018 85b43000
480bd01c 00000000
480bd020 8558a000
480bd024 00000000
480bd028 00000000
480bd02c 00000000
480bd030 00000000
480bd034 00000000
480bd038 00000000
480bd03c 00000000
480bd040 00000000
480bd044 00000000
480bd048 00000000
480bd04c 00000000
480bd050 00000000
480bd054 00000000
480bd058 00000000
480bd05c 00000000
480bd060 00000000
480bd064 00000000
480bd068 00000000
480bd06c 00000000
480bd070 00000000
480bd074 00000000
480bd078 00000000
480bd07c 00000000
480bd080 00000000
480bd084 00000000
480bd088 00000000
480bd08c 00000000
480bd090 00000000
480bd094 00000000
480bd098 00000000
480bd09c 00000000
480bd0a0 00000000
480bd0a4 00000000
480bd0a8 00000000
480bd0ac 00000000
480bd0b0 00000000
480bd0b4 00000000
480bd0b8 00000000
480bd0bc 00000000
480bd0c0 00000000
480bd0c4 00000000
480bd0c8 00000000
480bd0cc 00000000
480bd0d0 00000000
480bd0d4 00000000
480bd0d8 00000000
480bd0dc 00000000
480bd0e0 00000000
480bd0e4 00000000
480bd0e8 00000000
480bd0ec 00000000
480bd0f0 00000000
480bd0f4 00000000
480bd0f8 00000000
480bd0fc 00000000
480bd100 00000000
480bd104 00000000
480bd108 00000000
480bd10c 00000000

ISP
480bc004 00001000
480bc008 00000001
480bc00c 00000000
480bc010 82100000
480bc014 00000000
480bc018 82100000
480bc01c 00000000
480bc020 00000000
480bc024 00000000
480bc028 00000000
480bc02c 00000000
480bc030 00000000
480bc034 00000000
480bc038 00000000
480bc03c 00000000
480bc040 203ff300
480bc044 00000000
480bc048 00000000
480bc04c 00000000
480bc050 d8801084
480bc054 00000000
480bc058 00000000
480bc05c 00000000
480bc060 00000000
480bc064 00000000
480bc068 00000000
480bc06c 00000000
480bc070 00000000
480bc074 00000000
480bc078 00000000
480bc07c 00000000
480bc080 00000000
480bc084 00000000
480bc088 00000000
480bc08c 00000000
480bc090 00000000
480bc094 00000000
480bc098 00000000
480bc09c 00000000
480bc0a0 00000000
480bc0a4 00000000
480bd0a4 00000000
480bd0a8 00000000
480bd0ac 00000000
480bd0b0 00000000
480bd0b4 00000000
480bd0b8 00000000
480bd0bc 00000000
480bd0c0 00000000
480bd0c4 00000000
480bd0c8 00000000
480bd0cc 00000000
480bd0d0 00000000
480bd0d4 00000000
480bd0d8 00000000
480bd0dc 00000000
480bd0e0 00000000
480bd0e4 00000000
480bd0e8 00000000
480bd0ec 00000000
480bd0f0 00000000
480bd0f4 00000000
480bd0f8 00000000
480bd0fc 00000000
480bd100 00000000
480bd104 00000000
480bd108 00000000
480bd10c 00000000

Hi all

I looking for example code,

I have the EVB from mistral omap 30xx,

I connected to the camera interface connector a raw data from Sony CCD (the FPGA make the raw no translation).

I need hint how to start get the war data and display on the LCD.

Regards,

Doron sandroy

Tonson Lab