Other Parts Discussed in Thread: TCI6638K2K
Hi,
I have a few basic question about prefetching.
Currently, I have some data in L2 memory, that I want to move to MSRAM. I have read in ‘K2 SOC memory performance.doc’ that using if I use prefetching, and a small stride of 16kbytes, I can expect similar latency.
In the corepac manual, I can read in the chapter 7 ‘extended memory controller (XMC)’ that there is a bit to set in MARREG to enable prefetching for MSRAM. I have not read anything else about prefetching.
My questions are the following:
1. how prefetching is actually working? When the DSP is accessing the prefetchable data, since the memory zone is prefetchable, does in repeatedly read data in cache, when the current data in cache are being processed?
2. Do I need to add additional code lines when I actuallu process the data? In fact I would have expect comething like:
Prefetch data(some data)
Then When first data available
Loop
prefetch(new data)
Process(data)
End Loop
3. in the cache document, I can find a ‘Touch Assembly Routine’. Is the effect of this routine similar to prefeteching? Is this something that could in some way do the job as in my question 2?
Thanks for your anwers.
