AM5728: I/O connections prior to power up

Michael Shklyarman

Part Number: AM5728

Champs,

In a customer system AM5728 connects to FPGA over GPMC as well as DSS pins. The FPGA powers up before the CPU but the pins connecting to CPU remain tri-stated. The IO on the AM57x side aren't fail-safe, so the question is what is maximum current that can be sustained on the IO without causing any trouble for the CPU to power up and operate

thanks,

Michael

over 8 years ago

0 peaves over 8 years ago

TI__Guru 63235 points

Zero.

You should not source any potential to the IOs while the device is powered down.

Regards,
Paul

0 Don Schelle over 8 years ago in reply to peaves

TI__Expert 4150 points

Hi Paul,

What is the failure mechanism should current be sourced into the input?

Don

0 peaves over 8 years ago in reply to Don Schelle

TI__Guru 63235 points

The IOs were not designed for this use case and no analysis was performed to determine what happens.

Regards,
Paul

0 Michael Doyle over 8 years ago

Intellectual 710 points

Also, make sure your customer understands that the GPMC address/data pins are also used to determine what source the 5728 will boot to. Make sure those pins are pulled high/low as needed for the boot mode desired, and stable when PORz goes high, otherwise it might not boot at all (guess how I found that out!).

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AM5728: I/O connections prior to power up