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VCP2 with tail-biting

Curtis Rhodes
Prodigy 40 points
Other Parts Discussed in Thread: TMS320C6474

Hi,

I am interested in using the VCP2 peripheral to decode a convolutional code that uses tail-biting.  I see a couple of options for this in the "TMS320C6474 Chip Support Library API Reference Guide" in the VCP2_BaseParams struct:

Bool VCP2_BaseParams::tailBitEnable   

 

 

Enable/Disable tail biting

Uint16 VCP2_BaseParams::traceBackIndex   

 

 

Tailbiting traceback index mode

However, I see no reference to tail-biting in the VCP2 User's Guide (sprug20b).  I also see that in the CSL VCP2 overview, it states the VCP2 has tail-biting logic, however none of the control registers seem to allow me to access it.  Any thoughts would be greatly appreciated.

Thanks,

Curtis

  • 0
    Prodigy 80 points

    My VCP2 User's Guide document is spru972c -- have you tried perusing that one?  I'm sorry to say it's not very well-written, but it does have some useful information.  In particular, you may want to take a look at VCPIC5, as there is a field called "TB" (traceback mode), which can be set to 0x1 for "tailed traceback".  The CSL modifies this field when you set tailBitEnable.

  • 0 in reply to Colin54149
    Prodigy 80 points

    I just noticed you're not using a C645x chip, so your user's guide won't match mine.  However, the tail bit stuff may be the same.

  • 0 in reply to Colin54149
    Prodigy 40 points

    Thanks for the reply Colin.  I took a look at the CSL source, and setting tailBitEnable enables the ITBEN in VCPIC3. The ITBI field in the VPIC3 allows you to specify a start state for the beginning of the traceback processing phase, and the ITBEN enables the setting of this initial state.  Anyone know what happens if you do not enable ITBEN? Perhaps the traceback starts on the state with the highest calculated state metric (is this FMAXI?) ?

    With tailbiting the convolutional encoder state is initialized with the last N bits of the information frame during the encoding process, which forces it to start/end in the same state (instead of flushing the frame with 0s).  It seems that in a situation with an unknown start/end state, I would need to use the VCP2 with all of the possible states, and choose the result that has the best final FMAXS.

    Does anyone know if the VCP2 makes assumptions on start/end states?  It seems that if I was implementing a code that was guaranteed to be flushed with 0s at the end, I would always want to force ITBEN such that the traceback starts at a 0 state.  Additionally it seems that I would want to weigh the beginning branch metrics to force a 0 start state.

     

    Thanks,

    Curtis

  • 0 in reply to Curtis Rhodes
    Prodigy 40 points

    Any thoughts on the above questions would be greatly appreciated, but just wanted to clarify my main question.  Is there special logic on the VCP2 peripheral specifically for decoding tail-biting convolutional codes?  If not, is there a recommended implementation of this type of decode with the VCP2 peripheral?

     

    Thanks,

    Curtis

  • 0 in reply to Curtis Rhodes
    Prodigy 40 points

    Just an update on this post.  The parameters IMAXS and IMINS in VCPIC4 set the initial state metric for the desired start state and the rest of the states, respectively.  The desired start state is specified by IMAXI in VCPIC5.

    Now I'll throw this out there.  Is there any difference between convergent traceback mode and setting IMINS=IMAXS=0?  Not a whole lot of insight into the difference in algorithms in the sprug20b document.

     

    Thanks,

    Curtis