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66AK2H14: Total onchip PLLs present on the SOC

Madhu Sharma
Expert 2915 points
Part Number: 66AK2H14

Hi,

In 66AK2H14 datasheet, in page1, it is mentioned that there are Five On-Chip PLLs. I would like to know which are these PLLs.

I am confused with the PLLs because while going through the datasheet and hardware design guide I could notice more than 10 PLLs (Main PLL, System PLL, ARM PLL, DDR3APLL, DDR3BPLL, PASS PLL, SRIO PLL, AIF PLL, SGMII PLL,SRIO PLL, PCIE PLL, HYPERLINK 0 PLL, HYPERLINK 1 PLL, XFI PLL, USB PLL etc.).

Thanks & Regards,

Madhu.

  • 0
    TI__Guru**** 161600 points
    Hi Madhu,

    This is described in Section 10.5 of the device data manual. According to this section there are Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL and PASS PLL.
    The Hardware Design Guide is a common document, which tries to include all features of all Keystone II devices, to see what is available in each chip of the Keystone II family, you should refer to its specific Data Manual.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Expert 2915 points
    Hi Yordan,

    Thanks for the reply.

    If there are only 5 PLLs: Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL and PASS PLL,

    could you please let me know how the applied input clocks: HYP1CLK, HYP0CLK, PCIECLK, SRIOSGMIICLK will get multiplied/divided to get the required interface frequency ?

    Regards,
    Madhu.
  • 0 in reply to Madhu Sharma
    TI__Mastermind 46460 points

    Madhu,

    You are correct that there are many PLLs in the 66AK2H14 device.  Yordan listed for you the SOC-level PLLs: Main PLL, ARM PLL, DDR3APLL, DDR3BPLL, PASS PLL.  The Main PLL is also referred to as the System PLL since it generates the clocks for most of the SOC 'system' logic.

    There are also PLLs in the high performance SERDES interfaces as you listed: SRIO PLL, SGMII PLL, PCIE PLL, HYPERLINK 0 PLL, HYPERLINK 1 PLL, XFI PLL and USB  The AIF PLL interface is reserved in the 66AK2H14 device so the AIF PLL is not used.  These SERDES PLLs are specialized implementations for low phase jitter as needed by these multi-gigabit SERDES interfaces.

    All of the PLLs listed in my response are truly PLLs that must be programmed correctly and require proper input reference clocks.  The DDR3 interfaces also contain DLLs in each of the IP macro blocks but these are not programmable.

    Tom

  • 0 in reply to Tom Johnson 16214
    Expert 2915 points
    Hi Tom,

    Thanks a lot for the information.

    Could you please brief me how the SOC level PLLs are connected to SerDes PLLs?

    Section 10.5 of the datasheet ( figure 10-7) explains that SYSCLK1 output will be fed to all the peripherals including SGMII, Hyperlink and other multi-gigabit SERDES interfaces. So I am not able to understand why multi-gigabit SERDES interfaces have different PLLs.

    Thanks in advance.

    Regards,
    Madhu.
  • 0 in reply to Madhu Sharma
    Expert 2915 points
    HI,

    Correction for previous post:

    Section 10.5 of the datasheet ( figure 10-7) explains that SYSCLK1 output will be fed to all the peripherals including SGMII, Hyperlink and other multi-gigabit SERDES interfaces. So I am not able to understand why multi-gigabit SERDES PLLs require separate external inputs .

    Regards,
    Madhu
  • 0 in reply to Madhu Sharma
    TI__Mastermind 46460 points

    Madhu,

    SYSCLK1 and its divided derivatives are routed to many of the IP blocks, including the SERDES blocks, to enable data transfers over the internal switch fabric.  However, these clocks are not of the quality (i.e. phase jitter and accuracy) to be used for SERDES data communication.  Also, different SERDES interfaces have conflicting reference clock requirements.  Therefore, each SERDES interface has its own reference clock input.  This allows the customer to provide the quality of clock needed for the interface(s) that they choose to use.

    Tom

  • 0 in reply to Tom Johnson 16214
    Expert 2915 points

    Hi Tom,

    Thanks for the information.

    The SERDES clock inputs also have PLLs, which will vary the frequency. Whether this will reduce the clock quality ?

    Regards,

    Madhu.

  • 0 in reply to Madhu Sharma
    TI__Mastermind 46460 points

    Madhu,

    The SERDES PLLs are specialized to be able to multiply the input reference frequencies to provide clocks to the SERDES logic that allows the interface to meet the required specifications.  They are an integral part of the SERDES circuitry blocks.

    Tom