66AK2H14: PASS PLL input connection

Madhu Sharma

Part Number: 66AK2H14

Hi,

As per the datasheet of 66AK2H14 ( 307th page), PASS PLL can have two sources. One is PASSCLK(P|N) and other is output of main PLL mux.

Please let me know if there Is any improvement in SOCs performance if any one of the clock is used.

Also, Is there any chance that SYSCLK or output of PASS PLL will have more jitter or noise, if main PLL mux output is used as input to PASS PLL ?

Regards,

Madhu.

over 9 years ago

0 Yordan Kovachev over 9 years ago

TI__Guru**** 161600 points

Hi,

I've notified the design team. Their feedback will be posted here.

Best Regards,
Yordan

0 Senthilkumar Srinivasan over 9 years ago

TI__Mastermind 43660 points

Madhu,

The Packet Subsystem can operate up to 350MHz. Some systems use a CORECLK frequency that cannot be used by the PASSPLL to generate 350MHz causing some of the performance of that subsystem to be lost. For these systems the PASSCLK input can be used to allow the Packet subsystem to operate at it's highest rated speed. Most designs don't need the extra margin provided by using the optimum clock and can get close enough to 350MHz using the CORECLK.

Regards,
Senthil

0 Madhu Sharma over 9 years ago in reply to Senthilkumar Srinivasan

Expert 2915 points

Hi Senthil,

Thanks for the reply.

I am using 100MHz input to core clock.

As per table 8.27 of datasheet of 66AK2H14, it is possible to generate exact 350MHz from 100MHZ.

So I think separate input to PASS PLL pin is not required.

Please correct me if i am wrong.

Regards,

Madhu.

0 Senthilkumar Srinivasan over 9 years ago in reply to Madhu Sharma

TI__Mastermind 43660 points

Madhu,

When you could generate 350MHz from core clock, you are good to go.

Regards,
Senthil

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66AK2H14: PASS PLL input connection