TMS320C6678: .gel file customization

Hi,

I've notified the sw team. Their feedback will be posted here.

Best Regards,
Yordan

Hi,

If you run the C6678 standalone in no boot mode, we always recommend you runs the GEL to initialize the DSP. It configures main PLL, DDR, PA, SGMII, CPSW. The PA, SGMII and CPSW are related to your NDK.

For IPCGR0-7, it doesn't related to the GEL file. You can refer to processors.wiki.ti.com/.../Configuring_Interrupts_on_Keystone_Devices

The IPC interrupt number is 91 from Figure 7-32 TMS320C6678 System Event Inputs — C66x CorePac Primary.

Regards, Eric

Hi Eric,

We would like to know which parts of the gel file in particular are necessary in order to make the NDK work. Please, can you provide usmore detailed information (number of line, functions etc)?

It seems that the .gel file disables the IPC interrupt number 91(#define CSL_GEM_IPC_LOCAL            (0x0000005b))

We made an example project to prove it; you can find it attached to this reply.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/Notify_5F00_Test.7z

As you can see, cores 1-8 pend on a semaphore and Core0 wakes them using IPCGR0-7 interrupts. The related ISR calls the semaphore post on each core individually. In targetConfigs folder, you can find two target configuration file: one of them uses the gel file while the other runs program without it. You can observe the unexpected behaviour running the example with each of them.

Regards,

Giovambattista Astorino

Hi,

I am referring to the CCS 7.0.0 ccsv7\ccs_base\emulation\boards\evmc6678l\gel\evmc6678l.gel. It is version 2.0.0.5. Your CCS 6.2 GEL should be the same. All below function calls are necessary to run NDK:

Set_PSC_State(PD2, LPSC_PKTPROC, PSC_ENABLE);
Set_PSC_State(PD2, LPSC_CPGMAC, PSC_ENABLE);

/ Setup Pll3 pass clk @ 1050 MHz
Init_Pll3(PLLM_PASS, PLLD_PASS);

// Configure SGMII SERDES
configSGMIISerdes();

GEL_TextOut( "Configuring CPSW ...\n");
setCpSwConfig();

If you run NDK in DDR, you also need:

xmc_setup();
ddr3_setup_auto_lvl_1333(0);

For your IPC example, I have a quick look. For the one with GEL, why you run GEL on every core? Can you just run it on core 0 and check if IPC works or not?

Regards, Eric

Hi Eric,

Thanks for your fast and accurate reply. We will try to customize the gel file with these new information. Honestly we thought that the gel file had to be run on every core. Anyway, the behaviour is the same with the gel file loaded from core 0 only. IPC doesn't work.

Hi,

I tried your notify_test.out on all 8 cores, load then run at the same time. When this is no GEL file at all, I got "I'm awake!" for all 7 slave cores. When I have GEL file on core 0, I didn't get any notification.

Then I removed majority of the GEL file, kept Init_PLL(PLL1_M, PLL1_D) only to intialize the main PLL to 1GHz, I have some cores got notify, the others didn't. It looks some timing issue. This needs more time to look into.

Regards, Eric

Thanks for your help.

Just one more thing: we need the .gel file to use both network and ipc interrupt, so this constraint must be taken into account during .gel file customization.

Thanks a lot,

Giovambattista Astorino