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Linux/DRA744: Ethernet SMI BUS timing with Marvell 88E6390XA0

Ben Tseng
Intellectual 320 points
Part Number: DRA744

Tool/software: Linux

Hi 

I do connect two Ethernet device Microchip KSZ8081 and Marvell 88E6390XA0 together with MDIO/MDC of DRA744.

I can get KSZ8081 device information by mdio read command, but 88E6390XA0 just return error.

We also call help to Marvell FAE that FAE can get 88E6390XA0 device information with his fixture tool.

Then I try to measure the wave find the difference between KSZ8081  and 88E6390XA0.

After DRA744 was sent the register address, 88E6390XA0 has additional one high bit. as below picture.

Do any register setting can cover this difference? 

thank you

  • 0
    TI__Genius 15120 points

    Hi Ben,

    No register settings in DRA74x for the turnaround time (data ownership change-over).

    By MDIO standard, for read operations, <turnaround> time should be:

    - one 'idle' bit (no one drives data)

    - followed by one 'zero' bit driven by slave.

    This is followed by microchip, but not by marvell. Did you ask marvell for this behavior? I.e. why two idle bits wait instead of one?

    Regards,

    Stan

  • 0 in reply to Stanislav Stilyanov
    Intellectual 320 points

    Hi Stan,

    I asked the Marvell FAE that he tell me CPU read data needs after device pull MDIO down.

    If possible, Could you please share your MDIO standard data to me?


    Due to we also connect the MDC/MDIO to logic analyzer that logic analyzer can read these data on MDIO not error. 

    Do these idle bit will cause reading data error on DRA744?

    Thank you.

  • 0 in reply to Ben Tseng
    TI__Genius 15120 points

    Ben,

    To me, if told there must be two bits, that means 'pull MDIO down' must occur at the second bit clock.  I think they misunderstood the 'zero' bit as a 'start' bit. It is not true since MDIO is a synchronous bus, not an UART.

    TI MDIO IP is expecting exactly one idle and one zero bits. Seeing non zero bit at second clock means timeout or error.

    Excerpt from the TI MDIO spec:

    "An 'idle' bit time during which no device actively drives the MDIO signal shall be inserted

    between the register address field and the data field of a read frame in order to avoid

    contention. During a read frame, the PHY shall drive a 'zero' bit onto MDIO for the first bit time

    following the 'idle bit' and preceding the Data field. During a write frame, this field shall consist

    of a 'one' bit followed by a 'zero' bit."

    I did't do anything more than an internet search, but I did that many times before and I can tell <turnaround> (or TA) time is always two-bit in every document.

    For example, the below link is from ieee:

    www.ieee802.org/3/efm/public/sep01/turner_1_0901.pdf

    Regards,

    Stan

  • 0 in reply to Stanislav Stilyanov
    Intellectual 320 points

    Hi Stan,

    as you said "TI MDIO IP is expecting exactly one idle and one zero bits." that is mean the DRA744 perform MDIO read/write operation within 32 cycles.

    because of ST + OP + PHYADR + REGADR +TA +DATA = 32bit, right?

  • 0 in reply to Ben Tseng
    TI__Genius 15120 points

    I guess you are right. See the snapshot from the TRM below. Are you aware of any other formats than 32-bit?

  • 0 in reply to Stanislav Stilyanov
    Intellectual 320 points

    Hi Stan,

    I just get errata from Marvell that the 88E6390 may not return SMI Acknowledgment singal.(same as Bryant's mail)

    As below

    Is it possible fix this issue by hardware or software on DRA744?

  • 0 in reply to Ben Tseng
    TI__Genius 15120 points

    Hi Ben,

    I will write over the top-level steps here for other e2e guys. I must highlight that this is only an idea, I didn't test it.

    In hardware, I think to use 2 GPIO pins, one connected to MDIO data, other to MDIO clock.

    In Software, am interrupt routine would monitor and save the first 15 bits of MDIO frame. (MDIO bus sniffer)

    SW will test for <read> frame and PHY address we need.

    IF true, turn 'data' GPIO direction to output, low level (0) for exactly one bit time.

    That should trick the MDIO module that PHY acknowledges the request.

    Regards,

    Stan