TMS320C6678: DDR3 Dual Bank Design Issue

yimin bai34

Part Number: TMS320C6678

Hi Sir

We used C6678 for development and would like to use x16 4pcs DDR3. In the end ,we found MT41K1G16 (16Gbits, x16 TwinDie) and it has two ranks.

After checking below document, we found it needed Output clock to DRAMs (DDR3nCLKOUT0P/N, DDR3nCLKOUT1P/N) for dual bank design

PS: DDR3 Design Requirements for KeyStone Devices.pdf

But Micro DDR spec describes it only has one clk input. Can we leave DDRCLKOUT1 floating and only connect DDRCLKOUT0 with DDR3 CLK input pin.

thanks for your help.

Yimin

over 8 years ago

0 Yordan Kovachev over 8 years ago

TI__Guru**** 161600 points

Hi Yimin,

I've notified the hw team. Their feedback will be posted here.

Best Regards,
Yordan

0 Senthilkumar Srinivasan over 8 years ago

TI__Mastermind 43660 points

Yimin,

The KeyStone I DDR3 Initialization Application Report (SPRABL2D) was revised in January of 2015. It now contains instructions for configuring the Controller and PHY to support twin-die SDRAMs. This was not validated on any TI reference design but we provided this guidance as a service to customers eager to try it. Based on feedback from those who implemented this, we believe that this configuration is valid.

When you are using twin die SDRAM, please terminate the unused DDR clock as instructed in the hardware design guide.

Regards,
Senthil

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TMS320C6678: DDR3 Dual Bank Design Issue