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Hardware : J5Eco(DRA6xx) Display- Configuring Clock Frequency & Horizontal Frequency ( Horizontal blanking area )

Gokul Kujulva
Genius 4465 points

Hi all,

We are working in J5Eco(DRA6xx). We have flickering issue in the display.  

Our hardware team suggest to configure Clock Frequency & Horizontal Frequency  ( Horizontal blanking area ) .

What are the registers to be used for configuration ?

  1. Reducing clock frequency  from 28,341MHz to 37,4 MHz .
  2. Change Horizontal blanking area so that min horizontal frequency is 28.9kHz 26,8MHz/28.9KHz = < 927 (Horizontal period area)

Thanks & regards

Gokul

  • 0
    TI__Mastermind 42515 points
    Hi Gokul,

    I have forwarded your question to a DSS expert.

    Regards,
    Yordan
  • 0 in reply to Yordan Kamenov
    Prodigy 50 points
    Hi,

    Any suggestion on this.

    Regards,
    Kiran
  • 0 in reply to Kiran Gadi
    TI__Guru**** 170625 points

    Hi Kiran, Gokul,

    You can try to change/adjust clock frequencies through sysfs of the HDVPSS driver:

    processors.wiki.ti.com/.../TI811X_PSP_VPSS_VIDEO_Driver_User_Guide

    The VPSS driver supports the following features:
    Supports various Video PLL frequency through sysfs

    See "timings" and "mode" sysfs entries.

    You can also change clock frequencies through the clock framework:
    processors.wiki.ti.com/.../TI811X_PSP_PM_CLOCK_FRAMEWORK_User_Guide

    You can also check the below wiki regarding "flickering"
    processors.wiki.ti.com/.../TI811X_PSP_04.07.00.02_Release_Notes

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Prodigy 50 points
    Hi Pavel,

    Re-describing the problem to have specific suggestion.

    As mentioned above, we are debugging a screen flickering issue.

    As per the h/w team analysis, minimum horizontal frequency measured was 27.24KHz
    which is out of display specification of 28.9KHz and blanking measured was 197blanks.
    This measurement was done with active spread spectrum.

    So, we need to change the horizontal frequency from 27.24KHz to 28.9KHz. As per
    h/w team suggestion, horizontal frequency can be modified by the following two ways,

    1. Reduce the clock frequency dynamic from 28,341MHz to 37,4 MHz with spread spectrum enabled.

    2. Change the Horizontal blanking area so that minimum horizontal frequency is 28.9kHz.

    Please provide your suggestions on the same.

    And also we believe below two registers are to be looked into to configure the required horizontal frequency
    1. VIDEO1PLL_FRACCTRL
    2. VIDEO1PLL_CLKCTRL

    Please provide detailed description of both the registers, as we couldn't get much
    details on the SPRUGI5A_DRA6xx_TRM document.

    Hardware : J5Eco(DRA6xx)
    OS : QNX6.5
  • 0 in reply to Kiran Gadi
    Prodigy 50 points
    Hi,

    Please update, if you have anything.

    Regards,
    Kiran
  • 0 in reply to Kiran Gadi
    TI__Guru**** 170625 points

    Kiran Gadi said:
    Hardware : J5Eco(DRA6xx)
    OS : QNX6.5

    So you are not using our TI  EZSDK, but QNX. I will try to provide you some answers from J5Eco device side.

    Kiran Gadi said:
    As per the h/w team analysis, minimum horizontal frequency measured was 27.24KHz
    which is out of display specification of 28.9KHz and blanking measured was 197blanks.
    This measurement was done with active spread spectrum.

    So, we need to change the horizontal frequency from 27.24KHz to 28.9KHz. As per
    h/w team suggestion, horizontal frequency can be modified by the following two ways,

    1. Reduce the clock frequency dynamic from 28,341MHz to 37,4 MHz with spread spectrum enabled.

    2. Change the Horizontal blanking area so that minimum horizontal frequency is 28.9kHz.

    By "horizontal frequency" do you mean the frequency of the signal on VOUT[0]_HSYNC W25 pin?

    Kiran Gadi said:
    And also we believe below two registers are to be looked into to configure the required horizontal frequency
    1. VIDEO1PLL_FRACCTRL
    2. VIDEO1PLL_CLKCTRL

    These registers are used to configure VIDEO1 DPLL output clock. This clock is the HDVPSS VOUT0 pixel clock. By default in TI EZSDK it is configured for 148.5MHz to support 1920x1080@60 display resolution. See J5Eco TRM, section 2.3.6 Video Group Clock Structure

    Kiran Gadi said:
    Please provide detailed description of both the registers, as we couldn't get much
    details on the SPRUGI5A_DRA6xx_TRM document.

    Seems like you are using Jacinto5/DRA65x TRM, not J5Eco/DRA62x TRM. The documents you need to look at are:

    J5Eco/DRA62x TRM - SPRUHF4C
    J5Eco HDVPSS Users Guide - SPRUHG4B

    Regards,
    Pavel

     

  • 0 in reply to Pavel Botev
    Prodigy 50 points
    Hi Pavel,

    For your question, By "horizontal frequency" do you mean the frequency of the signal on VOUT[0]_HSYNC W25 pin?

    Yes, VOUT[0]_HSYNC W25 pin is for measuring the horizontal frequency.

    Please suggest the changes to achieve minimum horizontal frequency of 28.9KHz.


    Regards,
    Kiran
  • 0 in reply to Kiran Gadi
    Prodigy 50 points
    Hi Pavel,

    Any update on this please.

    Regards,
    Kiran
  • 0 in reply to Kiran Gadi
    TI__Guru**** 170625 points
    Kiran,

    As you are not using our HDVPSS Linux driver, you should perform direct HDVPSS registers settings update.

    For HDVPSS VOUT0/DVO2 we have many output pins, but let us focus on these two:

    VOUT[0]_CLK W26 - this is pixel clock, it is derived from DPLL_VIDEO1 and is also internally called hd_venc_g_clk and dvo_clk. It maximum frequency is 165MHz and is controlled by the DPLL_VIDEO1 registers (VIDEO1PLL_x).

    VOUT[0]_HSYNC W25 - Video Output Horizontal Sync output. This is the discrete horizontal synchronization output.

    From what I understand, you need to know how to control VOUT[0]_HSYNC signal (frequency/length/width). This signal is created and controlled from the DTG(Display Timing Generator), which is located inside HD_VENC module of the HDVPSS subsystem. This signal is controlled by the HD_VENC_D_CFGx register (in example CFG15, CFG16, etc). For more information regarding HD_VENC and its registers refer to the J5Eco HDVPSS Users Guide:

    section 1.2.7 High-Definition Video Encoder (HD_VENC)
    section 1.3.9 HD_VENC_D Registers

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    TI__Guru**** 170625 points
    Kiran,

    There is also test code (GEL file + C file) available. It is not linux, it is bare metal programming, you can check how this HD_VENC is programmed:

    support.spectrumdigital.com/.../ -> Test Code ZIP file

    j5ecoevm/video_tests/lcd_test/
    j5ecoevm/tests-jamr21/lcd/

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    TI__Guru**** 170625 points
    See also below e2e thread:

    e2e.ti.com/.../547907

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    TI__Guru**** 478575 points
    Hi Kiran,


    There is a software interface to changing/setting horizontal blanking area and also for configuring video pll. I think it is better to use this software interfaces to change the settings..
    Please first use these interfaces for changing configuration.

    Regards,
    Brijesh