• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 2 answers
  • Subscribers 98 subscribers
  • Views 1221 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRA72XEVM: Unable to send command through QSPI.

Ameer Hamza
Intellectual 340 points
Part Number: DRA72XEVM


Dear all,

I am trying to write baremetal application for NOR Flash(S25FL128S) communicating through ti_qspi, without using any OS. Since the first step for flash programming is to read the device/manufacturer id, but i am unable to read it. S25FL128S Data sheet says that I need to send command 0x90/0x9f in order to get the device id, but the problem is that there there is no sequence mentioned in the reference manual to send the commands. However i used the workflow by, enabled clock by programming QSPI_INTC_EOI_REG, programmed QSPI_SPI_DC_REG register to 0xF90000 [4-pin Single Read, 32-bits word length, Single Frame], programmed QSPI_SPI_DATA_REG to 0x29F [3 byte address, 9f Device ID command]. But i did not had anything on the Data Register (which I expect that Device ID would receive). If some one could please mention the workflow of sending commands from the QSPI would be very greatful. Thanks in advance.

Best Regards,

Hamza.

  • 0
    TI__Mastermind 42515 points
    Hi,

    I have forwarded your question to QSPI expert.

    Regards,
    Yordan
  • 0 in reply to Yordan Kamenov
    Intellectual 340 points
    Thanks you. Looking forward for their reply. :)
  • 0 in reply to Ameer Hamza
    TI__Expert 7885 points

    Hi

    Are you using TI-EVM or custom board ? 

    Please refer to U-boot code as reference. Make sure pin-mux are configured properly.

    pin-mux:

    board/ti/dra7xx/mux_data.h

    clkctrl :

     refer enable_basic_clocks() in arch/arm/cpu/armv7/omap5/hw_data.c

    qspi driver @

    drivers/spi/ti_qspi.c 

     

    Regards

    Ravi

  • 0 in reply to Ravi B
    Intellectual 340 points
    Hi Ravi,

    Thanks alot for your response. Yes I am using custom board and somehow got the device id, However I got a little question. I was confused about the FLEN bit for register QSPI_SPI_CMD_REG. I kinda figured about the WLEN. But I have not figured about the Frame Length yet, if you could describe it ?

    Thanks,
    Hamza.
  • 0 in reply to Ameer Hamza
    TI__Mastermind 42515 points
    Hi Hamza,

    The FLEN field is used to configure the number of words transferred in a read or write.

    From the TRM:
    The QSPI supports long transfers through a frame-style sequence. In its generic SPI use mode, a word
    can be defined up to 128 bits and multiple words can be transferred during a single access. For each
    word, a device initiator must read or write the new data and then tell the QSPI to continue the current
    operation. Using this sequence, a maximum of 4096 128-bit words can be transferred in a single SPI read
    or write operation. This allows great flexibility when connecting the QSPI to various types of devices.


    Regards,
    Yordan