We are trying get the Ethernet port working on our custom board, and we are not able to get the Network Coprocessor to successfully initialize. We are following the sequence in section 2.3.3 of the PSC User’s Guide (SPRUGV4C) to turn on the power domain and clock modules, but the PTSTAT.GOSTAT[X] bit never clears:
The procedure for concurrent power domain/module state transitions follows (X denotes the power domain number, Y denotes the module domain number):
1. Wait for PTSTAT.GOSTAT[X] to clear to 0x0. Wait for any previously initiated transitions to finish before initiating a new transition.
2. Set PDCTL[X].NEXT for an ON (0x1) transition.
3. Set MDCTL[Y].NEXT to Enable (0x3). Note that you may set transitions in multiple MDCTL.NEXT fields in this step as long as the corresponding power domain is on.
4. Set PTCMD.GO[X] 0x1 to initiate the state transition(s). The PSC will turn on the logic / memory for that particular domain, starts the module clock, then de-asserts the module reset.
5. Wait for PTSTAT.GOSTAT[X] to clear to 0x0. The domain is safely in the new state only after PTSTAT.GOSTAT[X] is cleared to 0x0.
We ran the same sequence on both our board and the K2E EVM. The K2E EVM completes initialization (PTSTAT.GOSTAT[2] goes to 0), but ours does not. The only known relevant difference between the two boards is that the EVM uses the NETCPCLK for an input clock to the NETCP PLL, and we use the CORECLK at the same frequency. We are at a loss for why this is occurring. We are at a standstill on ideas for what could be the problem. Please make suggestions on steps we can take to figure out what is going wrong!
Collected Data:
Below is pasted an annotated session from a configuration attempt on our board. The point of failure is highlighted in bold:
?
*** Commands ***
w - read 32-bit memory location
W - write 32-bit memory location
? - display menu
// Read registers associated with Power and Clock for NETCP control.
> w
32-bit hex address: 02620358 // NETCPPLLCTL0 - NETCP Pll Control Register 0
0x02620358: 0x090804C0
> w
32-bit hex address: 0262035c // NETCPPLLCTL1 - NETCP PLL Control Register 1
0x0262035C: 0x00002040
> w
32-bit hex address: 02350128 // PTSTAT - Status of transition
0x02350128: 0x00000000
// Turn on the NETCP power and enable the three clocks
> W
32-bit hex address: 02350308 // Set bit 0 of PDCTL2 - power on
32-bit value to write: 1
0x02350308: 0x00000001
> W
32-bit hex address: 02350a1c // Set bits 4:0 of MDCTL7 to 3 - enable state
32-bit value to write: 103
0x02350A1C: 0x00000103
> W
32-bit hex address: 02350a20 // Set bits 4:0 of MDCTL8 to 3 - enable state
32-bit value to write: 1103
0x02350A20: 0x00001103
> W
32-bit hex address: 02350a24 // Set bits 4:0 of MDCTL9 to 3 - enable state
32-bit value to write: 103
0x02350A24: 0x00000103
> W
32-bit hex address: 02350120 // Set bit 2 to cause NETCP command transition
32-bit value to write: 4
0x02350120: 0x00000004
> w
32-bit hex address: 02350128 // PTSTAT should read 0 for completion of command; 0x4 if not done
0x02350128: 0x00000004
// Read registers associated with Power and Clock for NETCP control.
> w
32-bit hex address: 235081c // MDSTAT7 - PA clock status - bits 5:0 should be 0x3
0x0235081C: 0x00000A18
> w
32-bit hex address: 2350820 // MDSTAT8 - Ethernet SGMIIs clock status - bits 5:0 should be 0x3
0x02350820: 0x00000A18
> w
32-bit hex address: 2350824 // MDSTAT9 - SA clock status - bits 5:0 should be 0x3
0x02350824: 0x00000A18
> w
32-bit hex address: 2350208 // PDSTAT2 - NETCP power status - bit 0 should be 1
0x02350208: 0x00000301
Below is pasted an annotated session from a similar configuration attempt on the K2E EVM board. The same point that failed on our board is highlighted in bold, except it passes on the EVM. Note that the EVM’s Ethernet port works out of boot, and we take some steps to turn the power domain and clock modules off before running the above initialization sequence to turn them back on:
U-Boot 2013.01 (Jun 11 2015 - 10:06:42)
I2C: ready
SPD csum OK; in SPD: 33 CC; computed 00000033 CC
DDR3A Speed will be configured for 1600 Operation.
Detected SO-DIMM [18KSF51272HZ-1G6K2]
DDR3 speed 1600
DRAM: 4 GiB
Reseting entire DDR3 memory to 0 ...
DRAM: 2 GiB
NAND: 512 MiB
Net: K2E_EMAC0, K2E_EMAC1, K2E_EMAC2, K2E_EMAC3, K2E_EMAC4, K2E_EMAC5, K2E_EMAC6, K2E_EMAC7
Hit any key to stop autoboot: 3 2 0
K2E EVM # ping 147.24.130.42
Using K2E_EMAC0 device
host 147.24.130.42 is alive
// Read ID register to see address base is good.
K2E EVM # md.l 0x2350000 1 // PID register 0x4482 in upper 16 bits, lower unknown
02350000: 44827200 .r.D
// Read all registers associated with Power and Clock for NETCP control.
K2E EVM # md.l 0x2350120 // PTCMD - Command transition
02350120: 00000000 ....
K2E EVM # md.l 0x2350128 // PTSTAT - Status of transition
02350128: 00000000 ....
K2E EVM # md.l 0x2350208 // PDSTAT2 - NETCP power status
02350208: 00000301 ....
K2E EVM # md.l 0x2350308 // PDCTL2 - NETCP power command
02350308: 00000001 ....
K2E EVM # md.l 0x235081c // MDSTAT7 - PA clock status
0235081c: 00001f03 ....
K2E EVM # md.l 0x2350820 // MDSTAT8 - Ethernet SGMIIs clock status
02350820: 00001f03 ....
K2E EVM # md.l 0x2350824 // MDSTAT9 - SA clock status
02350824: 00001f03 ....
K2E EVM # md.l 0x2350a1c // MDCTL7 - PA clock command
02350a1c: 00000103 ....
K2E EVM # md.l 0x2350a20 // MDCTL8 - Ethernet SGMIIs clock command
02350a20: 00001103 ....
K2E EVM # md.l 0x2350a24 // MDCTL9 - SA clock command
02350a24: 00000103 ....
K2E EVM # md.l 0x2620358 // NETCPPLLCTL0 - NETCP Pll Control Register 0
02620358: 090804c0 ....
K2E EVM # md.l 0x262035c // NETCPPLLCTL1 - NETCP PLL Control Register 1
0262035c: 00002040 @ ..
// Turn off the three NETCP clocks, then power
K2E EVM # md.l 0x2350128 // PTSTAT should read 0 to start
02350128: 00000000 ....
K2E EVM # mw.l 0x2350a1c 0x100 1 // Clear bits 4:0 of MDCTL7 - SwRstDisable state
K2E EVM # mw.l 0x2350a24 0x100 1 // Clear bits 4:0 of MDCTL7 - SwRstDisable state
K2E EVM # mw.l 0x2350a20 0x1100 1 // Clear bits 4:0 of MDCTL8 - SwRstDisable state
K2E EVM # mw.l 0x2350308 0x0 1 // Clear bit 0 of PDCTL2 - power off
K2E EVM # mw.l 0x2350120 0x4 1 // Set bit 2 to cause NETCP command transition
K2E EVM # md.l 0x2350128 // PTSTAT should read 0 for completion of command; 0x4 if not done
02350128: 00000000 ....
// Read all registers associated with Power and Clock for NETCP control.
K2E EVM # md.l 0x2350120 // PTCMD - Command transition
02350120: 00000000 ....
K2E EVM # md.l 0x2350128 // PTSTAT - Status of transition
02350128: 00000000 ....
K2E EVM # md.l 0x2350208 // PDSTAT2 - NETCP power status - bit 0 should be 0
02350208: 00000200 ....
K2E EVM # md.l 0x2350308 // PDCTL2 - NETCP power command
02350308: 00000000 ....
K2E EVM # md.l 0x235081c // MDSTAT7 - PA clock status - bits 5:0 should be 0
0235081c: 00000a00 ....
K2E EVM # md.l 0x2350820 // MDSTAT8 - Ethernet SGMIIs clock status - bits 5:0 should be 0
02350820: 00000a00 ....
K2E EVM # md.l 0x2350824 // MDSTAT9 - SA clock status - bits 5:0 should be 0
02350824: 00000a00 ....
K2E EVM # md.l 0x2350a1c // MDCTL7 - PA clock command
02350a1c: 00000100 ....
K2E EVM # md.l 0x2350a20 // MDCTL8 - Ethernet SGMIIs clock command
02350a20: 00001100 ....
K2E EVM # md.l 0x2350a24 // MDCTL9 - SA clock command
02350a24: 00000100 ....
K2E EVM # md.l 0x2620358 // NETCPPLLCTL0 - NETCP Pll Control Register 0
02620358: 090804c0 ....
K2E EVM # md.l 0x262035c // NETCPPLLCTL1 - NETCP PLL Control Register 1
0262035c: 00002040 @ ..
// Turn on the NETCP power and enable the three clocks
K2E EVM # md.l 0x2350128 // PTSTAT should read 0 to start
02350128: 00000000 ....
K2E EVM # mw.l 0x2350308 0x1 // Set bit 0 of PDCTL2 - power on
K2E EVM # mw.l 0x2350a1c 0x103 // Set bits 4:0 of MDCTL7 to 3 - enable state
K2E EVM # mw.l 0x2350a20 0x1103 // Set bits 4:0 of MDCTL8 to 3 - enable state
K2E EVM # mw.l 0x2350a24 0x103 // Set bits 4:0 of MDCTL9 to 3 - enable state
K2E EVM # mw.l 0x2350120 0x4 // Set bit 2 to cause NETCP command transition
K2E EVM # md.l 0x2350128 // PTSTAT should read 0 for completion of command; 0x4 if not done
02350128: 00000000 ....
// Read all registers associated with Power and Clock for NETCP control.
// At this point, the register hopefully should be back to what they were
// originally.
K2E EVM # md.l 0x2350120 // PTCMD - Command transition
02350120: 00000000 ....
K2E EVM # md.l 0x2350128 // PTSTAT - Status of transition
02350128: 00000000 ....
K2E EVM # md.l 0x2350208 // PDSTAT2 - NETCP power status - bit 0 should be 1
02350208: 00000301 ....
K2E EVM # md.l 0x2350308 // PDCTL2 - NETCP power command
02350308: 00000001 ....
K2E EVM # md.l 0x235081c // MDSTAT7 - PA clock status - bits 5:0 should be 0x3
0235081c: 00001f03 ....
K2E EVM # md.l 0x2350820 // MDSTAT8 - Ethernet SGMIIs clock status - bits 5:0 should be 0x3
02350820: 00001f03 ....
K2E EVM # md.l 0x2350824 // MDSTAT9 - SA clock status - bits 5:0 should be 0x3
02350824: 00001f03 ....
K2E EVM # md.l 0x2350a1c // MDCTL7 - PA clock command
02350a1c: 00000103 ....
K2E EVM # md.l 0x2350a20 // MDCTL8 - Ethernet SGMIIs clock command
02350a20: 00001103 ....
K2E EVM # md.l 0x2350a24 // MDCTL9 - SA clock command
02350a24: 00000103 ....
K2E EVM # md.l 0x2620358 // NETCPPLLCTL0 - NETCP Pll Control Register 0
02620358: 090804c0 ....
K2E EVM # md.l 0x262035c // NETCPPLLCTL1 - NETCP PLL Control Register 1
0262035c: 00002040 @ ..
