Linux/TMDXIDK5718: PCIe card issue

Cecile AUTRUSSON

Part Number: TMDXIDK5718

Tool/software: Linux

I plugged a PCIe ethernet board on my 5718IDK on J52. Since my ethernet device has a connector *1, I shall use A1-11 and B1-11. My board seems to start correctly, since leds correspond to the phy negociation. But I can't drive it from my kernel.

I specified status "okay" on axi0 to get pci express active . lspci displays the TI bridge 104c:8888. But no further device is detected. I try rescan but still no ethernet device is detected.

I looked at the schematics and saw that on a connector *1, it seems that there is a link between i2C and pci express.

What could be missing in my dts or kernel config?

Here are some traces :

[    0.482569] pci_bus 0000:01: fixups for bus
[    0.482576] PCI: bus1: Fast back to back transfers enabled
[    0.482584] pci_bus 0000:01: bus scan returning with max=01
[    0.482590] >> PCI Bus 0000:01
[    0.482601] pci 0000:00:00.0: scanning [bus 01-01] behind bridge, pass 1
[    0.482613] pci_bus 0000:00: bus scan returning with max=01
[    0.482674] pci 0000:00:00.0: fixup irq: got 466
[    0.482683] pci 0000:00:00.0: assigning IRQ 466
[    0.482714] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff]
[    0.482728] pci 0000:00:00.0: BAR 1: assigned [mem 0x20020000-0x2002ffff]
[    0.482741] pci 0000:00:00.0: PCI bridge to [bus 01]
[    0.482962] pcieport 0000:00:00.0: Signaling PME through PCIe PME interrupt
[    0.482975] pcie_pme 0000:00:00.0:pcie01: service driver pcie_pme loaded
[    0.483093] aer 0000:00:00.0:pcie02: service driver aer loaded

Can anybody help me about this problem?

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

The PCIe experts have been notified. They will respond here.

0 Rex Chang over 8 years ago in reply to Biser Gatchev-XID

TI__Guru 50170 points

Hi, Cecile,

AM571x-IDK had some issue before and I need to get more info from you.

1) Are you using TI AM571x-IDK?

2) Which ProcSDK release are you using?

There is an ECN issued against PCIe power delivery on existing AM571x-IDK which prevented us from testing the PCIe feature in the past until recently.

Besides this, was the PCIe card driver enabled in the kernel? Please review the PCIe Debugging page, http://processors.wiki.ti.com/index.php/PCIe_Debugging, on Connecting to the 3rd party PCIe Endpints as the example.

Once I have your ProcSDk release version, I can give it a try to see if I reproduce the issue.

Rex

0 Cecile AUTRUSSON over 8 years ago in reply to Rex Chang

Prodigy 120 points

Hello Rex,
I use a TI AM571x-IDK. My Linux version is linux-rt-4.4.41+gitAUTOINC+968d071ce9-g968d071ce9.
I check my final device tree by translating in text version:
axi@0 {
compatible = "simple-bus";
#size-cells = <0x1>;
#address-cells = <0x1>;
ranges = <0x51000000 0x51000000 0x3000 0x0 0x20000000 0x10000000>;

pcie_rc@51000000 {
compatible = "ti,dra7-pcie";
reg = <0x51000000 0x2000 0x51002000 0x14c 0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
interrupts = <0x0 0xe8 0x4 0x0 0xe9 0x4>;
#address-cells = <0x3>;
#size-cells = <0x2>;
device_type = "pci";
ranges = <0x81000000 0x0 0x0 0x3000 0x0 0x10000 0x82000000 0x0 0x20013000 0x13000 0x0 0xffed000>;
#interrupt-cells = <0x1>;
num-lanes = <0x1>;
linux,pci-domain = <0x0>;
ti,hwmods = "pcie1";
phys = <0xa8>;
phy-names = "pcie-phy0";
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 0xa9 0x1 0x0 0x0 0x0 0x2 0xa9 0x2 0x0 0x0 0x0 0x3 0xa9 0x3 0x0 0x0 0x0 0x4 0xa9 0x4>;
status = "okay";

interrupt-controller {
interrupt-controller;
#address-cells = <0x0>;
#interrupt-cells = <0x1>;
linux,phandle = <0xa9>;
phandle = <0xa9>;
};
};
};

And Phy is declared as
pciephy@4a094000 {
compatible = "ti,phy-pipe3-pcie";
reg = <0x4a094000 0x80 0x4a094400 0x64>;
reg-names = "phy_rx", "phy_tx";
syscon-phy-power = <0xeb 0x1c>;
syscon-pcs = <0xeb 0x10>;
clocks = <0x58 0x59 0xec 0xed 0xee 0x5d 0x10>;
clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", "div-clk", "phy-div", "sysclk";
#phy-cells = <0x0>;
linux,phandle = <0xa8>;
phandle = <0xa8>;
status = "okay";
};

1---> My ethernet board is well powered on since its ethernet phy led behaves as standard requirements.
2---> Even if I had a wrong ethernet driver, the PCI interface of this board shall return its PCI descriptor to be identified as Endpoint and I should see it by running lspci. No?
3---> I have kernel error messages during kernel initialization. I added traces on dra7-pcie driver access to controller registers.
I don't see any error except that link is never UP.

I checked PHY PIPE3 PCIE is initialized with success.
[ 0.452189] dra7-pcie 51000000.pcie_rc: GPIO lookup for consumer (null)
[ 0.452198] dra7-pcie 51000000.pcie_rc: using device tree for GPIO lookup
>>>>>>>>>> [ 0.452209] of_get_named_gpiod_flags: can't parse 'gpios' property of node '/ocp/axi@0/pcie_rc@51000000[0]'
>>>>>>>>>> [ 0.452219] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/ocp/axi@0/pcie_rc@51000000[0]'
>>>>>>>>>> [ 0.452227] dra7-pcie 51000000.pcie_rc: using lookup tables for GPIO lookup
>>>>>>>>>> [ 0.452236] dra7-pcie 51000000.pcie_rc: lookup for GPIO (null) failed
[ 0.452340] PCI host bridge /ocp/axi@0/pcie_rc@51000000 ranges:
[ 0.452350] No bus range found for /ocp/axi@0/pcie_rc@51000000, using [bus 00-ff]
[ 0.452382] IO 0x20003000..0x20012fff -> 0x00000000
[ 0.452408] MEM 0x20013000..0x2fffffff -> 0x20013000
[ 0.452612] write @f087c000 + offset 24: ffff80c0
[ 0.452620] write @f087c000 + offset 28: 7f3f
[ 0.452628] write @f087c000 + offset 34: ffffffe0
[ 0.452634] rd @f087c000 + offset 24: 6000
[ 0.452643] write @f087c000 + offset 24: 6000
[ 0.452654] write @f087c000 + offset 38: 1f
[ 0.452662] rd @f087c000 + offset 10c: 0
[ 0.452668] rd @f087c000 + offset 104: 0
[ 0.452674] write @f087c000 + offset 104: 1
[ 0.452680] rd @f087c000 + offset 104: 1
[ 0.452686] rd @f087c000 + offset 10c: 0
>>>>>>>>>> [ 0.482197] dra7-pcie 51000000.pcie_rc: link is not up
[ 0.482366] dra7-pcie 51000000.pcie_rc: PCI host bridge to bus 0000:00
[ 0.482379] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 0.482389] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 0.482399] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff]
[ 0.482409] pci_bus 0000:00: scanning bus
[ 0.482442] pci 0000:00:00.0: [104c:8888] type 01 class 0x060400
[ 0.482470] rd @f087c000 + offset 24: 4000
[ 0.482477] write @f087c000 + offset 24: 4000
[ 0.482498] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff]
[ 0.482519] pci 0000:00:00.0: reg 0x14: [mem 0x00000000-0x0000ffff]
[ 0.482565] pci 0000:00:00.0: calling pci_fixup_ide_bases+0x0/0x68
[ 0.482604] pci 0000:00:00.0: supports D1
[ 0.482613] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[ 0.482624] pci 0000:00:00.0: PME# disabled
[ 0.482823] pci_bus 0000:00: fixups for bus
[ 0.482837] PCI: bus0: Fast back to back transfers disabled
[ 0.482847] pci 0000:00:00.0: scanning [bus 01-01] behind bridge, pass 0
[ 0.482960] pci_bus 0000:01: scanning bus
[ 0.482969] rd @f087c000 + offset 10c: 0
[ 0.482977] pci_bus 0000:01: fixups for bus
[ 0.482983] PCI: bus1: Fast back to back transfers enabled
[ 0.482991] pci_bus 0000:01: bus scan returning with max=01
[ 0.482997] >> PCI Bus 0000:01
[ 0.483008] pci 0000:00:00.0: scanning [bus 01-01] behind bridge, pass 1
[ 0.483020] pci_bus 0000:00: bus scan returning with max=01
[ 0.483083] pci 0000:00:00.0: fixup irq: got 466
[ 0.483091] pci 0000:00:00.0: assigning IRQ 466
[ 0.483122] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff]
[ 0.483135] pci 0000:00:00.0: BAR 1: assigned [mem 0x20020000-0x2002ffff]
[ 0.483147] pci 0000:00:00.0: PCI bridge to [bus 01]
[ 0.483373] pcieport 0000:00:00.0: Signaling PME through PCIe PME interrupt
[ 0.483387] pcie_pme 0000:00:00.0:pcie01: service driver pcie_pme loaded
[ 0.483500] aer 0000:00:00.0:pcie02: service driver aer loaded
There is nothing detected behind the bridge.

4 - The bridge = pcie - Phy, No ??

0 Cecile AUTRUSSON over 8 years ago in reply to Cecile AUTRUSSON

Prodigy 120 points

Do you have any idea? I read all the article on TI website. But I can't see even if it might be a basic error in dts. Thank for your help.

0 Rex Chang over 8 years ago in reply to Cecile AUTRUSSON

TI__Guru 50170 points

HI, Cecile,

I am trying to set up for the test. I may not have the exact PCIe card as yours, but my goal is to check if an EP can be enumerated on IDK using ProcSDK 3.3 release.

Rex

0 Rex Chang over 8 years ago in reply to Rex Chang

TI__Guru 50170 points

Hi, Cecile,

Sorry for the slow response. It took me a while to get the setup working. I use ProcSDK 3.3.0.5 RT Linux, and modified am571x-idk.dts file to enable the pcie1_rc with the following changes:

&vip1 {
status = "okay";
};

+ &pcie1_rc {
+ status = "okay";
+ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+ };

Unfortunately, I don't have an ethernet card, but using a SATA card. the following is the lspci output:

- 10:26:07 [INFO] Host: uname -a
- 10:26:07 [INFO] Target:
uname -a
Linux am57xx-evm 4.4.41-rt50-g968d071ce9 #1 SMP PREEMPT RT Wed Mar 29 18:18:40 EDT 2017 armv7l GNU/Linux
root@am57xx-evm:~#

|TRACE LOG|Inside do_cmd:CMD=lspci -nn|
00:00.0 PCI bridge [0604]: Texas Instruments Device [104c:8888] (rev 01)
01:00.0 SATA controller [0106]: ASMedia Technology Inc. ASM1062 Serial ATA Controller [1b21:0612] (rev 01)
=============Output of lspci -vv==============
|TRACE LOG|Inside do_cmd:CMD=lspci -vv|
00:00.0 PCI bridge: Texas Instruments Device 8888 (rev 01) (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 432
Region 0: Memory at 20100000 (32-bit, non-prefetchable) [size=1M]
Region 1: Memory at 20020000 (32-bit, non-prefetchable) [size=64K]
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 00001000-00001fff
Memory behind bridge: 20200000-202fffff
Prefetchable memory behind bridge: 20300000-203fffff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity+ SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0+,D1+,D2-,D3hot+,D3cold-)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+
Address: 00000000ae8db000 Data: 0000
Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00
DevCap: MaxPayload 256 bytes, PhantFunc 0
ExtTag- RBE+
DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
LnkCap: Port #0, Speed 5GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <512ns, L1 <64us
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd-
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
Capabilities: [100 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
Kernel driver in use: pcieport

01:00.0 SATA controller: ASMedia Technology Inc. ASM1062 Serial ATA Controller (rev 01) (prog-if 01 [AHCI 1.0])
Subsystem: ASMedia Technology Inc. Device 1060
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 433
Region 0: I/O ports at 1020 [size=8]
Region 1: I/O ports at 1030 [size=4]
Region 2: I/O ports at 1028 [size=8]
Region 3: I/O ports at 1034 [size=4]
Region 4: I/O ports at 1000 [size=32]
Region 5: Memory at 20200000 (32-bit, non-prefetchable) [size=512]
[virtual] Expansion ROM at 20300000 [disabled] [size=64K]
Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit-
Address: ae8db000 Data: 0001
Capabilities: [78] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [80] Express (v2) Legacy Endpoint, MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <1us, L1 <8us
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM not supported, Exit Latency L0s <512ns, L1 <2us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR-, OBFF Not Supported
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
Capabilities: [100 v1] Virtual Channel
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
Arb: Fixed- WRR32- WRR64- WRR128-
Ctrl: ArbSelect=Fixed
Status: InProgress-
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
Status: NegoPending- InProgress-
Kernel driver in use: ahci
Kernel modules: ahci

0 Rex Chang over 8 years ago in reply to Rex Chang

TI__Guru 50170 points

Hi, Cecile,

Just to correct my ProcSDk version. It is 3.3.0.4 rt linux. sorry for the confusing.

Rex

0 Cecile AUTRUSSON over 8 years ago in reply to Rex Chang

Prodigy 120 points

Hi Rex,

I reinitialized my config with

I changed my dts and get the correct dtb as you suggested me .

Linux am57xx-evm 4.4.41-rt50-g968d071ce9 #164 SMP Wed Jun 14 13:48:26 CEST 2017 armv7l GNU/Linux

But still I can not see my pci device.

SO you have a 5718IDK rev 1.3B?

When I look at the hardware scheme on http://www.ti.com/lit/df/sprr242/sprr242.pdf, , it looks like PCIe reset is on GPIO 5.

I can send you my config.gz if you want. There is no am571x-idk-defconfig . I did all what was suggested in the tutorials . But I can't see the problem...

0 Rex Chang over 8 years ago in reply to Cecile AUTRUSSON

TI__Guru 50170 points

Hi, Cecile,

I am not sure why PCIe EP is not detected in your case. I am using an AM571x-IDK PG2.0 rev 1.3a, but it has latest ECN populated to resolve the power issue. It is equivalent to rev 1.3c. But it doesn't apply to you because you don't have the symptom which IDK stalls during the boot.

To build am571x-idk, you should follow instruction for am57xx family, but rt variant. The defconfig is tisdk_am57xx-evm-rt_defconfig. I used kernel and filesystem from ProcSDK 3.3.0.4 Linux RT. So, I only needed to build the dtb file with PCIe enabled to run the test.

2029 make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- tisdk_am57xx-evm-rt_defconfig
2030 make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- am571x-idk.dtb

Rex

0 Cecile AUTRUSSON over 8 years ago in reply to Rex Chang

Prodigy 120 points

Hello Rex,
I've just started again to test my am5718idk today . I tried all what you suggested me. But I still can not see my board.
I saw another article in e2e site that was dealing with clock problem. Do you know if I could have any pb with that?
Does your device need 3.3V?

0 Cecile AUTRUSSON over 8 years ago in reply to Cecile AUTRUSSON

Prodigy 120 points

Here is my lspci -vv
00:00.0 PCI bridge: Texas Instruments Device 8888 (rev 01) (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 432
Region 0: Memory at 20100000 (32-bit, non-prefetchable) [size=1M]
Region 1: Memory at 20020000 (32-bit, non-prefetchable) [size=64K]
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity+ SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0+,D1+,D2-,D3hot+,D3cold-)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
Address: 0000000000000000 Data: 0000
Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00
DevCap: MaxPayload 256 bytes, PhantFunc 0
ExtTag- RBE+
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
LnkCap: Port #0, Speed 5GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <512ns, L1 <64us
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd-
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
Capabilities: [100 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
Kernel driver in use: pcieport

Compared to you :
The following lines are missing

I/O behind bridge: 00001000-00001fff
Memory behind bridge: 20200000-202fffff
Prefetchable memory behind bridge: 20300000-203fffff

Also : Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
Address: 0000000000000000 Data: 0000

What do you think?
I also tried with already compiled kernel and filesystem with my modified Dts.

0 Cecile AUTRUSSON over 8 years ago in reply to Cecile AUTRUSSON

Prodigy 120 points

Indeed I finished by measuring the inputs on the connector.
3.3 and 3.3 aux are correct.
But I have no 12V.
It seems that only two connectors use 12V : J37 and J52. Both have no 12V.
Do you have any idea?

0 Cecile AUTRUSSON over 8 years ago in reply to Rex Chang

Prodigy 120 points

Actually I added MSI support etc, I had a problem on 12V on one board but my device does not need it.
Has your SATA controller a PCI express connector with 18 pins?

0 Tom Johnson 16214 over 8 years ago in reply to Cecile AUTRUSSON

TI__Mastermind 46460 points

Cecile,

U79 is designed to generate +12V from the +5V VMAIN external supply. If you do not have any +12V at pin 2 of J37 or pins B1 or A2 of the PCIe connector J52, that board must be faulty. Do you se any missing or damaged components around U79?

Tom

0 Rex Chang over 8 years ago in reply to Tom Johnson 16214

TI__Guru 50170 points

Cecile,

The SATA PCIe card used in our test is a SIIG DP SATA 6Gbps 2-port PCIe SATA controller card (SC-SA0L11-S2), https://www.amazon.com/SIIG-Express-Controller-SC-SA0L11-S2-Asmedia/dp/B00UYNHYVQ

Rex

Processors

Processors forum

Linux/TMDXIDK5718: PCIe card issue