Tool/software: Linux
I need a simple continuous PWM signal out the AM335x gpmc_ad8 [gpio0_22] pin. No sync needed, and all timing/start is not critical, since this only drives an LCD backlight for brighness - just need somethingi in the 1Khz ballpark with a few duty cycle settings. The TRM (spru73o pdf) examplefigure 15-27 pg2308 is about perfect. I can't install the BloaterWare PWM mess and don't have sysfs PWM features on the kernel I inherited. I can't seem to get the configuration right. Below is some psuedo code that defines my setup sequence. Anyone see what I'm missing? The pin just sits HI and never starts a pulse chain.
Thanks - Steve
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// Desired continous PWM out gpmc_ad8/gpio0_22 pin, no sync needed.
// Format is write_some_pwm_base_register[OFFSET] |= VALUE
// Most defines are named as per StarterWare
//
#define SOC_CONTROL_REGS 0x44E10000 // trm pg1411
#define PWM_CLOCK_ENABLE 0x2
#define PWMSS_CLOCK_CONFIG 0x08
#define PER_EPWMSS0_CLKCTRL_OFFSET 0xd4
#define PER_EPWMSS1_CLKCTRL_OFFSET 0xcc
#define PER_EPWMSS2_CLKCTRL_OFFSET 0xd8
#define CONTROL_PWMSS_CTRL 0x0664 // trm pg1449
#define CONTROL_CONF_GPMC_AD(n) (0x0800 + (n * 4))
#define CONTROL_CONF_GPMC_AD8 0x0820
#define SOC_PWMSS0_REGS 0x48300000
#define SOC_PWMSS1_REGS 0x48302000
#define SOC_PWMSS2_REGS 0x48304000 // this is PWM2 base addresses needed
#define SOC_ECAP_REGS 0x00000100
#define SOC_EQEP_REGS 0x00000180
#define SOC_EPWM_REGS 0x00000200 // ePWM reg offset
#define SOC_EPWM_2_REGS (SOC_PWMSS2_REGS + SOC_EPWM_REGS) // epwm2 base
#define PWMSS_CLOCK_CONFIG 0x08
#define PWMSS_EHRPWM_CLK_EN_ACK 0x0100
#define PWMSS_CTRL_PWMSS2_TBCLKEN 0x04
// EPWMx init registers
#define EHRPWM_TBCTL 0x0 // select up or dwn count, select clock, etc.
#define EHRPWM_TBSTS 0x2
#define EHRPWM_TBPHSHR 0x4
#define EHRPWM_TBPHS 0x6 // used to clear the phase reg
#define EHRPWM_TBCTR 0x8 // this should be TBCNT, used to clear the TB counter reg
#define EHRPWM_TBPRD 0xA // period reg in TBCLK counts
#define EHRPWM_CMPCTL 0xE // set shadow modes
#define EHRPWM_CMPAHR 0x10
#define EHRPWM_CMPA 0x12 // A compare reg in clock counts
#define EHRPWM_CMPB 0x14
#define EHRPWM_AQCTLA 0x16
#define EHRPWM_AQCTLB 0x18
/**************************************
* pwm en register base addr 0x44E00000
**************************************/
printf ("Enabling PWM2");
write_per_regs[PER_EPWMSS2_CLKCTRL_OFFSET] = PWM_CLOCK_ENABLE;
/***********************************
* pwm register base addr 0x44E10000
***********************************/
printf ("setting pinmux CTRL \n");
// set pinmux for gpio0_22,gpmc_ad8 to mode4
// write [0x44E10000 + 0x820] |= 0x14; // pin mode4 should be ehrpwm2a, pullup enable
write_pwm_regs[CONTROL_CONF_GPMC_AD8] |= 0x14; // pin mode4 should be ehrpwm2a, pullup enable
// enable time base clock for pwm2, 44E10000 + 664 |= 4, trm pg1449
// write [0x44E10000 + 0x664] = 0; // enable all pwm2 tbclks's
write_pwm_regs[CONTROL_PWMSS_CTRL] |= ~PWMSS_CTRL_PWMSS2_TBCLKEN;
/**********************************
* pwm2 register base is 0x48304000
**********************************/
printf ("pwm2 timing setup \n");
// enable clocks, 48304000 + 08 |= 100
write_pwm2_regs[PWMSS_CLOCK_CONFIG] |= PWMSS_EHRPWM_CLK_EN_ACK;
// setup TBPRD, x48304200 + 0x0A, trm pg2376
write_pwm2_regs[SOC_EPWM_REGS + EHRPWM_TBPRD] |= 0x04; // as per trm example figure 15-27, pg2308
// clear TBPHS, trm pg2374, resets to 0, but should clear.
write_pwm2_regs[SOC_EPWM_REGS + EHRPWM_TBPHS] = 0x0;
// clear TBCNT, trm pg2374, restets to 0.
write_pwm2_regs[SOC_EPWM_REGS + EHRPWM_TBCTR] |= 0x0;
// setup TBCTL, trm pg2370, [0x48304000 + 0x200 + 0] |= 0xCB2, CTRMODE=2, CLKDIV=3
write_per_regs[SOC_EPWM_REGS + EHRPWM_TBCTL] |= 0x0CB2; // trm ex figure 15-27
// set compare values both A & B, although don't need B. trm pg2380
write_pwm2_regs[SOC_EPWM_REGS + EHRPWM_CMPA] |= 0x02;
write_pwm2_regs[SOC_EPWM_REGS + EHRPWM_CMPB] |= 0x02;
// set CMPCTL, should reset to 0.
// set AQCTLx registers, trm pg2382, CAU=2, CAD=1, CBU=2, CBD=1.
write_pwm2_regs[SOC_EPWM_REGS + EHRPWM_AQCTLA] |= 0x0660;
write_pwm2_regs[SOC_EPWM_REGS + EHRPWM_AQCTLB] |= 0x0660;
