omap3530 power sequence

Laurie Verboort

Other Parts Discussed in Thread: OMAP3530

I’ve got a question, What if the sys_nrespwron pin comes up with the vdds and vdds_mem and is stable at 1.8 volts for about 200us. See attached omap3530_CUS_power_up_sequence.bmp. It is then held low until VDD_core is brought up and then toggled. Would this cause the system to be locked in a kind of reset state?

The TEK0003 shows the same pins but is after a quick power cycle. How do I add attachments.? thanks..

over 15 years ago

0 kshin over 15 years ago

TI__Genius 16690 points

Hello Laurie,

Could you also tell me how vdds_wkup_bg, vdds_sram, vdds_dpll_dll, vdds_dpll_per and vdd_mpu_iva are ramped up during the power sequence ? Please refer this design note for attaching a file.

Regards,

Kazunobu Shin

0 Laurie Verboort over 15 years ago

Prodigy 190 points

0 kshin over 15 years ago in reply to Laurie Verboort

TI__Genius 16690 points

Hi Laurie,

sys_nrespwron should be held low till all vdds, vdds_mem, vdds_wkup_bg, vdds_sram, vdds_dpll_dll, vdds_dpll_per, vdd_core, vdd_mpu_iva and input clocks are stabilized. it can't be toggled during this sequence.

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omap3530 power sequence