Other Parts Discussed in Thread: SYSBIOS
I have a custom design where we are streaming samples from an FPGA to our C6657 DSP over the UPP Interface.
Our sample rate is relatively slow (76.8 Khz)
This effective clock rate of 76.8 KHz * 16 = 1.2288 MHz. (in our multi channel mode)
I am attempting to start and stop the samples as needed (on-demand).
When I initially start the samples (the first run of the UPP after boot), things work properly
When the samples are stopped, subsequent calls to start the samples generate UORI errors. This almost feels like the upp/dma logic is trying to resume a prematurely terminated transfer.
A couple other key pieces of information.
1) to stop the samples the interrupts enabled are turned off with the UPIEC register
2) After those interrupts are disabled, the dma is cleared, by writing 0x1F in the UPIS2 register
3) The code appears to timeout while waiting for the ACT bit (bit 0) in the UPIS2 register to go low
4) After that timeout, we do a SW reset of the upp
a. Set the UPPCR EN bit to 0
b. We wait for the UPPCR DB bit to be equal to 0
c. Set the SWRST bit in UPPCR to 1 (putting the UPP into reset)
d. Delay 300 us
e. Set the SWRST bin in the UPPCR to 0 (taking the UPP out of reset)
f. Delay 300 us
Our "line size" is set to roughly 2.5 ms, with 2 lines per window (5 ms Window)
Should the ACT bit be going low after writing to the UPIS2? Is there any reason it would remain "stuck" active?
Am I doing something wrong when trying to stop and start the samples (ie is there a different or more graceful way to terminate the UPP stream)?
The ISR for the UPP/DMA is only reading the status and posting SysBios Events to a Task which handles, pulling samples from the DMA buffers and storing them into a buffer that is used to process them.
