DM6446 video subsystem

a simplified version of VPFE pipeline (omitting some HW blocks) would be   CCD ---> Previewer ----> resizer

Sure.  When data is brought it thru CCD, it can go directly to SDRAM or Preview engine.  As a matter of fact, at each stage of video pipeline, you can program the data to go directly to SDRAM or the next processing block.  I belive by default, our drivers send data to SDRAM between each processing block.  You may want to familiarize yourself with our VPFE User Guide (http://focus.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=sprue38e) as well as our Video capture driver included in DVSDK software (V4L2 driver).

Thanks.

My data is brought  thru  CCD. Then,  it  go directly to  SDRAM.

DM6446  use  DMA   to write  data  into  SDRAM.  

Then   DSP   CPU  can  read  data  from  SDRAM   into   DSP's    RAM.

 Does  DMA  give  some signal   to  CPU   (arm or dsp)  to  tell    CPU  that   data  has  been  written  into   SDRAM ??

The most common used interrupt when doing video processing is VSYNC, which marks the end of a video frame captured (or displayed).  Once this happens, you can pass frame thru resizer, previwer... usually in less time than it takes to capture hte next frame. 

I  want  to  store some  data into SDRAM from VPFE( just use CCDC of VPFE )  use  DMA .  Does  data flow  is  SBL  to  SDRAM  ???

From a hardware perspective you need to 1) configure CCDC to tell it video size and format to capture, 2) you need to program a hardware register in VPFE that tells CCDC where place incoming data (memory pointer to buffer in SDRAM), and 3) enable VPFE and the data coming in via CCDC will be automatically placed starting at the SDRAM address you programmed into the register.  Thruout the entire VPSS (both VPFE and VPBE), a dedicated video DMA engine is always enabled (no need to mess with EDMA).  Therefore CCDC to SDRAM data will use video DMA; if resizer later wants to read data from SDRAM resize and write back to SDRAM (two hardwareregisters specify source and destination SDRAM addresses), DMA will also be used automatically behind the scenes.

From a software perspective: V4L2 is your Linux capture driver; per this Linux standard, the user space application tells the driver how many capture buffers to allocate (allows implementation of double buffering, tripple buffering.... or more); the user space application also tells the drivers which buffers it can have to place incoming data in and which buffers the application is currently working on (say writting data from SDRAM to file) so that driver does not interfere with those buffers.  The driver underneath takes care of programming the hardware register with the different SDRAM memory pointers for all the buffers it manages.

Thank you for your  detailed description.

Now  I kown DMA  used in VPSS is a  dedicated  video  DMA  engine .

We  can use some space  in  SDRAM  as  buffer.

There  is  a   Shared  Buffer  Logic (SBL) in VPSS.  Is  the  data  flow  SBL  to  SDRAM??

Does  the  buffer  you say   refer  to  SBL or  buffer  in  SDRAM??

How can I kown the size of  buffer??

Can  I  programm  it??

Is  there  a   document  that  I can  refer to  ??

Can  I  refer to   SPRU629F (  TMS320C  DSP  Video Port/VCXO  Interpolated  Control(VIC)  Reference  Guide )  ??

I was referring to buffer is SDRAM, the dedicated video DMA engine which is always enabled reads/writes data from/to SDRAM.  There are read/write fifos built into some VPSS hardware blocks that can impose limits (example: max line-length preview engine can handle); there are also error overflow/underflow error bits that are set to manage data in the VPSS hardware.

That said, you sort of do control size of buffer... you tell the hardware the size of your video frame (e.g. NTSC, 720p, custom size...) and give it a buffer pointer that has enough space to hold a video frame of that size.  As data is captured or move from one VPSS bock to another, you can adjust the size and SDRAM memory pointer (different register for each block) and the hardware is smart enough to capture the appropriate amount of data into the buffer you gave it.

The best documents that describe VPSS hardware are the VPBE User guide and VPFE User Guide (both available at the product folder: http://focus.ti.com/docs/prod/folders/print/tms320dm6446.html )

thank you .

Now   the  most  important  problem  I  concern is  this :

   When   the  dedicated  DMA engine  start  transfer  data  ??

  When   the  dedicated  DMA  engine  complete  the  transfer ??

Has  some  signal  or   status  field  indicate  the  start and  complete ??

And  I  can not   find  any  answer   in  VPFE User guide and  VPBE   User  guide .  In  fact ,  I  have read  them  about  several times.

Normally the reads and writes will start as soon as you enable the specific hardware block.  For the first (capture port) and last (display port) hardware block writes/reads to SDRAM (via dedicated DMA) are synchronized by VSYNC, which marks the beginning of a new video frame.  For the capture portion, it does not matter if it is enabled in the middle of a frame or not, eventually it will sync up with the next VSYNC interrupt.   For all subsequent VPSS blocks, once you program the size of the frame it will read, you must ensure that valid data is already present in that input buffer, bacause as soon as is enabled, it will start reading the data.  There are status registers to let you know if there are undeflow or overflow conditions, but the video DMA is started automatically and ends when the size of input frame you programmed has been processed.

VPFE UG is probrably the best place to see the flow since most of the independant video hardware blocks are found there.