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TMS320C6657: Process of L1P Error Detection

g.f.
Guru 15520 points
Part Number: TMS320C6657

Hi,

I have questions about C6657.

Q1.
C6657 L1P cache are supporting Error Detection but it's not supporting Error Correction.
So, my customer want to know the soft error rate of L1P.
Is there any data of L1P soft error rate?

Q2.
If L1P soft error occured, is it possible to detect the address where the error occured
and is it possible to read from the real address?

Q3.
When the error interrupt will occur?
Is it just after reading the address where the error occur?
Or, will the error interrupt occur after executing the next instruction?

Q4.
If L1P soft error occured, will the cache be invalidated automatically then re-read from the real address
and the instruction which error occured will be executed again?

best regards,
g.f.

  • 0
    TI__Guru**** 161600 points
    Hi,

    I've notified the factory team. Their feedback will be posted here.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Guru* 95265 points
    Hi,

    This is TI page for soft error rate: www.ti.com/.../soft_error_rate_faqs.page I don't have detailed numbers for C6657. It also depends the environment if high radioactivity there.

    Please look at C66x corepac user guide: 11.2.1 L1P Error Detection Control Registers for L1PEDSTAT/CMD/ADDR registers for the info. It is logged in the L1PEDADDR.

    11.2.3 L1P Error Exception/Interrupt
    L1P provides one error detection exception output “L1P_ED” event. This exception is
    used to signal that a DMA parity error (DMAERR) was detected during a DMA/IDMA
    read access to L1P memory. This event is sent to the interrupt controller block in the
    CorePac, which can then route this to the DSP as interrupt or exception input, as
    appropriate.

    In turn, the DSP invalidates program code by flushing the content of the L1P Cache. This is done by ISR code.

    Regards, Eric
  • 0 in reply to lding
    Guru 15520 points
    Hi Eric,

    Thank you for the reply and I'm very sorry for the delay.

    I want to ask about the SER. I read the TI page which you attached.
    I understood that generally it is not tested and SER data are not provided from TI.
    But it seem that TI will provide SER estimator calculator if the customer concluded NDA, is it correct?
    How to get this SER estimator calculator, should I contact to local TI FAE?

    And I want the answer for following question which I poseted previously.
    I read the Corepac user guide, but I can find which timing the error interrupt will occur.
    >Q3.
    >When the error interrupt will occur?
    >Is it just after reading the address where the error occur?
    >Or, will the error interrupt occur after executing the next instruction?

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru* 95265 points
    Hi,

    For the SER estimator, please contact local FAE. For the timing when interrupt occurs, it happens just after reading the address.

    Regards, Eric
  • 0 in reply to lding
    Guru 15520 points
    Hi Eric,

    Thank you for the reply.
    I understood.

    best regards,
    g.f.