In TRM (SPRUH73P), Table 10-1 shows the required L3 connections between bus masters and slave ports and Figure 10-2 shows the L4 bus architecture and memory-mapped peripherals.
The bus masters access L4_PER through four ports (L4_PER Port 0 to 3) and various peripherals are connected to L4_PER.
Can all peripherals connected to L4_PER be accessed from all of four ports (L4_PER Port 0 to 3)?
Our customer wants to access GPIO registers by EDMA.
Best regards,
Daisuke
Hi Biser-san,
Thank you for your reply.
I do not mention the DMA request.
The customer wants to read or write the peripheral registers by using EDMA, not CPU (A8).
The EDMA Transfer Controllers (TPTC 0 to 2) use L4_PER Port 2 or L4_PER Port 3 to access the peripherals connected to L4_PER.
The answer to my question will make clear which peripheral registers EDMA can access.
Daisuke Maeda said:
Can all peripherals connected to L4_PER be accessed from all of four ports (L4_PER Port 0 to 3)?
Best regards,
Daisuke
