Part Number: TMS320C6678
I modified some code on example IPC interrupt project, first Core0 send a IPC interrupt to Core1, then Core1 send to Core2,thus finially Core7 send a interrupt to Core0.
In this case, each core should invoke a ISR, but in this project, some cores invoke more than one ISR. Where the problems is?
the interrupt function and main function are below:
#include <c6x.h>
#include <stdint.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <ti/csl/csl_chip.h>
#include <ti/csl/src/intc/csl_intc.h>
#include <ti/csl/csl_cpintcAux.h>
#include "ipc_interrupt.h"
void main(void) {
uint32_t i;
uint32_t cnt = 0;
uint32_t coreID = CSL_chipReadReg(CSL_CHIP_DNUM);
TSCL = 0;
intcInit();
registerInterrupt();
for (i=0; i<1000; i++)
{
cnt += 1;
}
if(coreID == 0)
{
IssueInterruptToNextCore();
}
while(1)
{
cnt += 1;
}
}
#ifndef IPC_INTERRUPT_H_
#define IPC_INTERRUPT_H_
#define MAX_CORE_NUM (8)
#define MAX_SYSTEM_VECTOR (8)
#define MAX_CORE_VECTOR (12)
/************************ USER DEFINES ********************/
#define CORENUM 8
#define IPCGR0 (0x02620240u)
#define IPCGR1 (0x02620244u)
#define IPCGR2 (0x02620248u)
#define IPCGR3 (0x0262024Cu)
#define IPCGR4 (0x02620250u)
#define IPCGR5 (0x02620254u)
#define IPCGR6 (0x02620258u)
#define IPCGR7 (0x0262025Cu)
#define IPCAR0 (0x02620280u)
#define IPCAR1 (0x02620284u)
#define IPCAR2 (0x02620288u)
#define IPCAR3 (0x0262028Cu)
#define IPCAR4 (0x02620290u)
#define IPCAR5 (0x02620294u)
#define IPCAR6 (0x02620298u)
#define IPCAR7 (0x0262029Cu)
#define INTC_EVENTID_IPC_LOCAL (91)
typedef struct
{
uint32_t core; // CoreID
uint32_t event; // INTC event
CSL_IntcVectId vect; // Core interrupt vector
CSL_IntcEventHandler isr;
}interruptCfg;
int32_t intcInit();
int32_t registerInterrupt();
void IssueInterruptToNextCore();
void IPC_ISR();
#endif /* IPC_INTERRUPT_H_ */
#include <stdint.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <ti/csl/csl_chip.h>
#include <ti/csl/src/intc/csl_intc.h>
#include <ti/csl/csl_cpintcAux.h>
#include "ipc_interrupt.h"
CSL_IntcGlobalEnableState state;
CSL_IntcContext context;
CSL_IntcEventHandlerRecord Record[CSL_INTC_EVENTID_CNT];
CSL_IntcEventHandlerRecord EventRecord;
uint32_t coreVector[MAX_CORE_NUM];
CSL_IntcObj intcObj[16];
CSL_IntcHandle hintc[16];
volatile Uint32 interruptNumber=0;
/* IPCGR Info */
int32_t iIPCGRInfo[CORENUM] = {
IPCGR0,
IPCGR1,
IPCGR2,
IPCGR3,
IPCGR4,
IPCGR5,
IPCGR6,
IPCGR7
};
/* IPCAR Info */
int32_t iIPCARInfo[CORENUM] = {
IPCAR0,
IPCAR1,
IPCAR2,
IPCAR3,
IPCAR4,
IPCAR5,
IPCAR6,
IPCAR7
};
interruptCfg intInfo[MAX_SYSTEM_VECTOR] =
{
/* core event vector*/
{ 0, 91, CSL_INTC_VECTID_4, &IPC_ISR},
{ 1, 91, CSL_INTC_VECTID_4, &IPC_ISR},
{ 2, 91, CSL_INTC_VECTID_4, &IPC_ISR},
{ 3, 91, CSL_INTC_VECTID_4, &IPC_ISR},
{ 4, 91, CSL_INTC_VECTID_4, &IPC_ISR},
{ 5, 91, CSL_INTC_VECTID_4, &IPC_ISR},
{ 6, 91, CSL_INTC_VECTID_4, &IPC_ISR},
{ 7, 91, CSL_INTC_VECTID_4, &IPC_ISR},
};
int32_t intcInit()
{
/* INTC module initialization */
context.eventhandlerRecord = Record;
context.numEvtEntries = CSL_INTC_EVENTID_CNT;
if (CSL_intcInit (&context) != CSL_SOK)
return -1;
/* Enable NMIs */
if (CSL_intcGlobalNmiEnable () != CSL_SOK)
return -1;
/* Enable global interrupts */
if (CSL_intcGlobalEnable (&state) != CSL_SOK)
return -1;
/* INTC has been initialized successfully. */
return 0;
}
int32_t registerInterrupt()
{
uint32_t i;
uint32_t event;
uint32_t vector;
uint32_t core;
uint32_t coreID = CSL_chipReadReg (CSL_CHIP_DNUM);
CSL_IntcEventHandler isr;
for (i=0; i<MAX_CORE_NUM; i++)
{
coreVector[i] = 0;
}
for (i=0; i<MAX_SYSTEM_VECTOR; i++)
{
core = intInfo[i].core;
if (coreID == core)
{
event = intInfo[i].event;
vector = intInfo[i].vect;
isr = intInfo[i].isr;
if (MAX_CORE_VECTOR <= coreVector[core])
{
printf("Core %d Vector Number Exceed\n");
}
hintc[vector] = CSL_intcOpen (&intcObj[vector], event, (CSL_IntcParam*)&vector , NULL);
if (hintc[vector] == NULL)
{
printf("Error: GEM-INTC Open failed\n");
return -1;
}
/* Register an call-back handler which is invoked when the event occurs. */
EventRecord.handler = isr;
EventRecord.arg = 0;
if (CSL_intcPlugEventHandler(hintc[vector],&EventRecord) != CSL_SOK)
{
printf("Error: GEM-INTC Plug event handler failed\n");
return -1;
}
/* clear the events. */
if (CSL_intcHwControl(hintc[vector],CSL_INTC_CMD_EVTCLEAR, NULL) != CSL_SOK)
{
printf("Error: GEM-INTC CSL_INTC_CMD_EVTCLEAR command failed\n");
return -1;
}
/* Enabling the events. */
if (CSL_intcHwControl(hintc[vector],CSL_INTC_CMD_EVTENABLE, NULL) != CSL_SOK)
{
printf("Error: GEM-INTC CSL_INTC_CMD_EVTENABLE command failed\n");
return -1;
}
coreVector[core]++;
}
}
return 0;
}
// BOOT and CONFIG dsp system modules Definitions
#define CHIP_LEVEL_REG 0x02620000
// Boot cfg registers
#define KICK0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0038)
#define KICK1 *(unsigned int*)(CHIP_LEVEL_REG + 0x003C)
#define KICK0_UNLOCK (0x83E70B13)
#define KICK1_UNLOCK (0x95A4F1E0)
#define KICK_LOCK 0
void IssueInterruptToNextCore()
{
uint32_t CoreNum;
uint32_t iNextCore;
static uint32_t interruptInfo=0;
CoreNum = CSL_chipReadReg (CSL_CHIP_DNUM);
iNextCore = (CoreNum + 1)%8; //
printf("Set interrupt from Core %x to Core %d, cycle = %d\n", CoreNum, iNextCore, TSCL);
interruptInfo +=16;
// Unlock Config
KICK0 = KICK0_UNLOCK;
KICK1 = KICK1_UNLOCK;
*(volatile uint32_t *) iIPCGRInfo[iNextCore] = interruptInfo;
*(volatile uint32_t *) iIPCGRInfo[iNextCore] |= 1;
// Unlock Config
KICK0 = KICK0_UNLOCK;
KICK1 = KICK1_UNLOCK;
printf("Interrupt Info %d\n", interruptInfo);
}
void IPC_ISR()
{
volatile uint32_t read_ipcgr;
uint32_t CoreNum;
uint32_t iPrevCore;
CoreNum = CSL_chipReadReg (CSL_CHIP_DNUM);;
iPrevCore = (CoreNum - 1)%8;
read_ipcgr = *(volatile Uint32 *) iIPCGRInfo[CoreNum];
*(volatile uint32_t *) iIPCARInfo[CoreNum] = read_ipcgr; //clear the related source info
printf("Receive interrupt from Core %d with info 0x%x, cycle = %d\n", iPrevCore, read_ipcgr, TSCL);
interruptNumber++;
if(CoreNum!=0)//
{
IssueInterruptToNextCore();
}
else
{
printf("IPC test passed!\n");
}
}
And this result is :
