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GPMC ECC setting for 4-bits ECC algorithm



I use these settings (

#define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS

#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
					  10, 11, 12, 13, 14, 15, 16, 17, \
					  18, 19, 20, 21, 22, 23, 24, 25, \
					  26, 27, 28, 29, 30, 31, 32, 33, \
					  34, 35, 36, 37, 38, 39, 40, 41, \
					  42, 43, 44, 45, 46, 47, 48, 49, \
					  50, 51, 52, 53, 54, 55, 56, 57, }

#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	14
) for NAND flash(MT29F2G16AADWP:D) in TI J6 EVM board. The setting was reference here=> https://lists.denx.de/pipermail/u-boot/2014-July/184174.html  

Currently, i can read/write/erase the flash successfully. But in our custom board, we'll replace this flash with new one(MT29F2G16ABAEAWP-AIT). Both size and bus width are the same, but the vendor says the old one use 1-bit ECC algorithm, and the new one use 4-bit ECC algorithm.

According to my setting, i am using OMAP_ECC_BCH8_CODE_HW, which mean up to 8 bits error correction.

So, should i modify setting to fit this new flash?

Regards,

Shawn