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AM3352: NAND flash problem

Ioannis Gragopoulos
Intellectual 340 points
Part Number: AM3352
Other Parts Discussed in Thread: TPS65217

Hello,

I am facing problems with the nand flash in a custom board. The nand chip is TOSHIBA TH58BVG3S0HTAI0. The nand operates OK from u-boot, but when I try to execute ubiattach from linux I get the following message:

ubiattach /dev/ubi_ctrl -m ,5
[ 2464.815719] ubi0: attaching mtd5
[ 2465.071990] ubi0: scanning is finished
[ 2465.075975] ubi0: empty MTD device detected
[ 2465.081179] ubi0 error: ubi_early_get_peb: no free eraseblocks
[ 2465.087968] ubi0 error: ubi_attach_mtd_dev: failed to attach mtd5, error -28
ubiattach: UBI_IOCATT: No space left on device

The dts configuration is:

nandflash_pins_s0: nandflash_pins_s0 {
pinctrl-single,pins = <
0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};

&gpmc {
pinctrl-names = "default";
pinctrl-0 = <&nandflash_pins_s0>;
ranges = <0 0 0x08000000 0x20000000>;
status = "okay";

nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>;
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE_NONE>;
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
ti,nand-ecc-opt = "bch8";
ti,nand-xfer-type = "polled";

gpmc,device-nand = "true";
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;

#address-cells = <1>;
#size-cells = <1>;
ti,elm-id = <&elm>;

partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000040000>;
};
partition@1 {
label = "NAND.u-boot";
reg = <0x00040000 0x00100000>;
};
partition@2 {
label = "NAND.u-boot-env";
reg = <0x00140000 0x00040000>;
};
partition@3 {
label = "NAND.dtb";
reg = <0x00180000 0x00040000>;
};
partition@4 {
label = "NAND.kernel";
reg = <0x001C0000 0x00800000>;
};
partition@5 {
label = "NAND.rootfs";
reg = <0x009c0000 0x3f640000>;
};
};
};

The output from kernel boot is:

[ 1.859673] omap-gpmc 50000000.gpmc: GPMC revision 6.0
[ 1.865450] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
[ 1.873889] nand: device found, Manufacturer ID: 0x98, Chip ID: 0xd3
[ 1.880695] nand: Toshiba NAND 1GiB 3,3V 8-bit
[ 1.885385] nand: 1024 MiB, SLC, erase size: 256 KiB, page size: 4096, OOB size: 128
[ 1.893573] nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
[ 1.904845] 6 ofpart partitions found on MTD device omap2-nand.0
[ 1.911268] Creating 6 MTD partitions on "omap2-nand.0":
[ 1.916886] 0x000000000000-0x000000040000 : "partition"
[ 1.931165] 0x000000040000-0x000000140000 : "partition"
[ 1.945078] 0x000000140000-0x000000180000 : "partition"
[ 1.955133] mmc0: host does not support reading read-only switch, assuming write-enable
[ 1.966589] 0x000000180000-0x0000001c0000 : "partition"
[ 1.975140] mmc0: new high speed SDHC card at address 0001
[ 1.985685] mmcblk0: mmc0:0001 TEAM 29.5 GiB
[ 1.996151] 0x0000001c0000-0x0000009c0000 : "partition"
[ 2.008685] mmcblk0: p1
[ 2.019145] 0x0000009c0000-0x000040000000 : "partition"
[ 2.328784] tps65217 0-0024: TPS65217 ID 0xe version 1.2
[ 2.334657] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz

I boot the device from nand (MLO, uboot, dtb, kernel) and I use rootfs from mmc. The nand chip has been erased from uboot with "nand erase.chip"

Thanks a lot,

Best Regards,

Ioannis

  • 0
    Guru 13660 points
    Hi Ioannis,

    1. Have you formatted/flashed ubifs inside the mtd5 partition ?
    2. Have you tried with -O option, which is pagesize ?
  • 0 in reply to Dwarakesh Radhakrishnan
    Intellectual 340 points

    Hi,

    thank you for the reply. I think that it is very early for format and ubifs. I am just trying to attach to an empty volume and is not working. It looks like a problem in nand configuration parameters (because the same chip is working from u-boot), but there are a  lot of them and I am lost.

    Best Regards,

    Ioannis

  • 0 in reply to Ioannis Gragopoulos
    Guru 13660 points
    Hi,

    What do you see as a result of the following command in linux
    # flash_eraseall /dev/mtd5

    You can dump the GPMC registers and compare them in uboot and in kernel for a quick difference.
  • 0 in reply to Dwarakesh Radhakrishnan
    Guru 13660 points

    Hi,
    I don't think it could be issue with NAND configuration yet. Basic configuration seems to be fine, since NAND ID is read in the kernel boot logs.
    If you are able to perform non-ubi operations like flash_eraseall successfully, then it could that you might need to format the partition as UBI volume.

  • 0 in reply to Dwarakesh Radhakrishnan
    Intellectual 340 points

    Hi,

    thank you for your effort. The strange about this flash chip is that it has 4096 page size and 128 bytes spare. I think that usually flash with 4096 bytes page has 224 bytes spare area. In order to make it work I did the following modifications to  CONFIG_SYS_NAND_ECCPOS in u-boot:

    £define CONFIG_ENV_IS_IN_NAND

    #define CONFIG_SYS_NAND_5_ADDR_CYCLE

    #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \

    CONFIG_SYS_NAND_PAGE_SIZE)

    #define CONFIG_SYS_NAND_PAGE_SIZE 4096

    #define CONFIG_SYS_NAND_OOBSIZE 128

    #define CONFIG_SYS_NAND_BLOCK_SIZE (256*1024)

    #define CONFIG_NAND_OMAP_GPMC

    #define CONFIG_NAND_OMAP_GPMC_PREFETCH

    #define CONFIG_NAND_OMAP_ELM

    #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS

    #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \

    16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \

    28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \

    40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, \

    52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \

    64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, \

    76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, \

    88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \

    100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \

    110, 111, 112, 113,}

    /*

    #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \

    10, 11, 12, 13, 14, 15, 16, 17, \

    18, 19, 20, 21, 22, 23, 24, 25, \

    26, 27, 28, 29, 30, 31, 32, 33, \

    34, 35, 36, 37, 38, 39, 40, 41, \

    42, 43, 44, 45, 46, 47, 48, 49, \

    50, 51, 52, 53, 54, 55, 56, 57, }

    */

    #define CONFIG_SYS_NAND_ECCSIZE 512

    #define CONFIG_SYS_NAND_ECCBYTES 14

    #define CONFIG_SYS_NAND_ONFI_DETECTION

    #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW

    Do you know if there is a similar definition in linux for eccpos, or it is computed automatically?

    Best Regards,

    Ioannis

  • 0 in reply to Ioannis Gragopoulos
    Guru 13660 points
    Hi,

    It is split and assigned in file: drivers/mtd/nand/omap2.c

    Check for it, eccpos in it.
  • 0 in reply to Dwarakesh Radhakrishnan
    Intellectual 340 points
    Hi again,
    I was reading again the datasheet from TOSHIBA TH58BVG3S0HTAI0. It seems that the flash chip has internal logic for hardware ecc. Does anybody knows, how I could disable the ecc from u-boot spl?

    Thanks.
  • 0 in reply to Ioannis Gragopoulos
    Guru 13660 points
    Hi,

    Are you sure Toshiba provides ECC hardware logic internally ? Generally NAND chip provides spare area, where the host controller(NAND controller in AM335x) can calculate and store the ECC.

    There is no easy way to disable ECC, since it is not confined under one single MACRO. The ecc code is by default enabled in processor SDK. What is your software package ?
  • 0 in reply to Dwarakesh Radhakrishnan
    Intellectual 340 points

    Hi,

    below is a copy-paste from the datasheet:

    The TH58BVG3S0HTAI0 has ECC logic on the chip and 8bit read errors for each 528Bytes can be corrected

    internally.... 8bit ECC for each 528Byte is implemented on the chip ......

    The software I use is ti-u-boot from git and openwrt for kernel and rootf. The kernel version is 4.4.14

    Best Regards,

    Ioannis

  • 0 in reply to Ioannis Gragopoulos
    Guru 13660 points
    Hi,

    That is something new for me. Thanks! Yeah looks like the NAND chip itself supports the ECC. I understand that you were able to make change in ecc layout and then get it working in uboot. I think thats the way forward, you need to try similar ECC layout in kernel too. It may not be easy to disable ECC in uboot, since there is no cleaner way in latest uboot to disable ECC for AM335x Board. Also looks like ECC calculation of NAND chip is not interfering with the ECC calculation from AM335x, since it worked in uboot, with ECC enabled. Is that correct ?. Check if there is a way to disable the NAND chip ECC.
  • 0 in reply to Dwarakesh Radhakrishnan
    Intellectual 340 points

    Hi,

    Yes it worked for uboot. The plan for tomorrow is to keep the ecc for u-boot and I will try it to disable it in kernel. I saw that there is a corresponding config in kernel menuconfig. Then I will try to erase the mtd partition from linux with flash_eraseall. It does't sound very promissing but I can't think of something else. Otherwise I will change the flash chip.

    Thanks a lot.

    Ioannis