• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 97 subscribers
  • Views 802 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM5718: Decoupling capacitors recommendations

Fredda
Intellectual 625 points
Part Number: AM5718

Chapter 8.4 in http://www.ti.com/lit/ds/sprs957d/sprs957d.pdf about PDN implementation guidance states that "TI supports only designs that follow the board design guidelines contained in the http://www.ti.com/lit/pdf/spraby8 application report.

This report deals with the AM572x MPUs and not the AM571x MPUs. Not a big problem, but what's more of a problem is the recommendations about the decoupling capacitors in table 2.

Supply 100 nF 220 nF 470 nF 1 uF 2.2 uF 4.7 uF 22 uF
vdd_mpu 12 2 2 3 1 1 1

These recommendations are not perfectly in line with the recommendations at http://processors.wiki.ti.com/index.php/General_hardware_design/BGA_PCB_design/BGA_decoupling that states that:

"Based on the fact that often differing values of capacitors cause more harm than good (because of the resonance possibility listed above), and the fact that with newer capacitor dielectrics, larger value capacitors have the nearly identical high frequency impedance as their smaller value counterparts in the same body size, we recommend using just one value, 0.1uF-0.2uF, in the smallest package manufacturable by your company (this should be 0402 size or smaller). "

Or are the > 100 nF capacitors to be considered as bulk capacitors?

In any case, it's interesting to note that the AM5718 reference design (http://www.ti.com/lit/df/sprr242/sprr242.pdf) definitely doesn't follow the above recommendations.

Different schools within TI?

Best Regards

/F

  • 0
    TI__Guru**** 393215 points
    The PDN experts have been notified. They will respond here.
  • 0
    TI__Mastermind 27890 points
    Fredda,
    Thanks for the feedback.

    It's impossible to provide a blanket "use x value caps in y numbers and your board will always meet the PDN requirements". There are simply too many variables that go into the successful implementation of a complex PCB + SoC to make this kind of determination so we provide the SoC requirements and generic guidelines based on a successful design as a starting point for PCB designers. In some cases through our own internal testing and simulations we find that some boards may need to deviate from these generic guidelines to optimize performance, which is what you are seeing when trying to compare different PCB designs against each other.

    Take a look at SPRAC76...it is a PDN analysis of the same SoC, but on a different PCB (AM572x IDK). The static and dynamic PCB requirements are the same, but pre-fab simulation of the board revealed that the cap count/values had to be changed from those of the AM572x GP EVM in order to meet the same SoC requirements. This further illustrates why it is so important that each PCB design be simulated prior to fabrication.
  • 0 in reply to -DK-
    Intellectual 625 points
    Thanks for the answer. I was hoping to get away without doing a PDN simulation by simply following some design rules, but I guess that is somewhat naive.

    But I still suspect that the designer of the AM5718 reference design belongs to the "old school" and that the starting point was to use a lot of different values of the decoupling capacitors. And in this particular case a PDN simulation showed that design met the requirements and that there were no resonances. It would have been interesting to see a comparison with a design that used the same values of the decoupling capacitors as a starting point. Well, just guesses from my side...

    Regards
    /F