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AM3359: CPSW in RMII mode on ICEv2

Mat Bennion
Intellectual 410 points
Part Number: AM3359


I'm trying to port my application based on the LWIP stack for the TMDSSK3358 to the AM335x ICE v2.1.  The key difference seems to be the PHY interface: on the TMDSSK3358, the CPSW EMAC's GMII interface is used.  This is not compatible with the AM335x ICE v2.1, where the RMII interface is used when driving the PHYs from the CPSW.

So my first question is: are there any examples of configuring the CPSW to connect to the PHYs on the ICE board (including pin muxing, configuring the RMII/MII muxes on the board, setting the MAC control register etc).  Ideally, this would be a bare-bones example like the wonderful LWIP stack - just calling into an API is less informative.

My second question is: the PDK comes with an EMAC driver (in my installation, it's here: C:\ti\pdk_am335x_1_0_5\packages\ti\drv\emac).  This might be a good starting point to answer my first question, but I can't see what assumptions it makes about the hardware.  Is it intended to work directly on the ICE v2.1 board?  This example is very unclear on what it's actually doing because it calls into so many other parts of the PDK code.

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Mastermind 43296 points
    Mat,

    pdk_am335x_1_0_6\packages\ti\transport\ndk\nimu is the example for AM335x ICE v2 CPSW you can refer to.

    The example CCS project can built with the pdkProjectCreate.bat script in pdk_am335x_1_0_6\packages, see build instruction here - processors.wiki.ti.com/.../Rebuilding_The_PDK

    Regards,
    Garrett
  • 0 in reply to Garrett Ding
    Intellectual 410 points
    Hi, thanks for the link. I've confirmed from the NIMU example that the PHY addresses on the ICE v2.1A boards are 1 and 3 (which matches the schematic).

    So my next question is: why is the MDIOALIVE register reading 0x00080008? This suggests that the PHYs are responding to addresses 3 and 19. Any ideas?
  • 0 in reply to Mat Bennion
    Intellectual 410 points
    Perhaps the real question is: where is the ICE hardware documented? For example, the NIMU example includes the following:

    void PhySetupAndReset(void)
    {
    /* PR1_MII_CTL */
    GPIO_write(GPIO_PIN_PR1_MII_CTRL, GPIO_PIN_VAL_HIGH);

    /* MUX MII CONTROL */
    GPIO_write(GPIO_PIN_MUX_MII_CTRL, GPIO_PIN_VAL_HIGH);

    /* FET SWITCH CONTROL */
    GPIO_write(GPIO_PIN_FET_SWITCH_CTRL, GPIO_PIN_VAL_HIGH);

    /* DDR VTT ENABLE */
    GPIO_write(GPIO_PIN_DDR_VTT_EN, GPIO_PIN_VAL_HIGH);

    /* Phy 0 & 1 reset */
    GPIO_write(GPIO_PIN_PHY_0_1_RST, GPIO_PIN_VAL_LOW);
    delay(100);
    GPIO_write(GPIO_PIN_PHY_0_1_RST, GPIO_PIN_VAL_HIGH);
    delay(100);
    }

    Each of these settings takes me a while to figure out from the schematics. Is there a description of what these signals are used for and how they should be set to make the board behave in different ways?
  • 0 in reply to Mat Bennion
    TI__Mastermind 43296 points

    Mat,

    You really should see 0x0000000A in MDIOALIVE register as below.

    The HW user guide is in the link:

    Regards, Garrett

  • 0 in reply to Garrett Ding
    Intellectual 410 points

    Hi, thanks for your reply.  I've now figured it all out.  The problem I had is that the HW User Guide does not contain all the information that is needed to operate the board.  Perhaps this information could be added to the Wiki?

    Here's what users need to know:

    1. The Sys Boot buffers (U37 and U38) need to be deactivated after boot to allow the PHYs to read the address selection lines.  Otherwise, they'll pick up values from the SYSBOOT pull-up/down resistors (this is specifically why my PHYs were picking up the wrong addresses).  After this, the PHYs need to be hard-reset to re-read the address selection lines.

    2. The FET switch (U4) needs to be deactivated (I think to disconnect some lines shared with the PRU-CSS)

    3. The MII muxes (U9 and U11) need to be set correctly - input "S" should be high.

    4. The PHY clock (U12) needs to be set up - the function ClockSynthesizerSetup in the NIMU example does this.

  • 0 in reply to Mat Bennion
    TI__Mastermind 43296 points
    Hi Mat,

    Thank for your feedback on the HW User Guide! I have forwarded your suggestions to HW team for review and considering to add in wiki.

    Regards,
    Garrett