TCI6638K2K: TCI6638K2K and Kintex Ultra Scale FPGA (XCKCU060 FFVA 1156 -2 E) SRIO communication

Hi 

We have built a board using  Kintex Ultrascale FPGA (XCKCU060 FFVA 1156 -2 E) and TCI6638K2K DSP. Both of the them have been designed to communicate using 4x Lane SRIO communication. There is no SRIO switch between them.

We have ported the SRIO throughput example with the modification as suggest in the attached document and found that the LOOPBACK SRIO THROUGHPUT test works fine using CORE 0 AND CORE 1. As you aware from the below thread that the RapidIO specification used are different in Keystone 2 compared to XILINX FPGA SRIO CORE.

https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/332001/1159652#1159652

FPGA is using the following specification.

• Designed to RapidIO Interconnect Specification rev. 2.2
• Supports 1x, 2x and 4x operation with the ability to train down to 1x from 2x or 4x
• Supports per-lane speeds of 1.25, 2.5,3.125, 5.0, and 6.25 Gbaud

I had few questions related to short and Long control symbol configuration. The configuration in FPGA exists but we were unable to trace the same in the following document

KeyStone Architecture
Literature Number: SPRUGW1B 
November 2012
Serial Rapid IO (SRIO)

Also when we invoked CCSL_IDEF_INLINE void CSL_SRIO_GetPortPLMImplSpecificControl API we found that both the IDLE1 and IDLE2 are set to zero. In fact all the contents of the structure were returned as zero

typedef struct SRIO_PLM_IMPL_CONTROL

{

    Uint8   payloadCapture;

    Uint8   useIdle2;

    Uint8   useIdle1;

    Uint8   dlbEn;

    Uint8   forceReinit;

    Uint8   softRstPort;

    Uint8   txBypass;

    Uint8   lineLoopbackMode;

    Uint8   portSelfReset;

    Uint8   selfReset;

    Uint8   swapTx;

    Uint8   swapRx;

    Uint8   dltThresh;

}SRIO_PLM_IMPL_CONTROL;

How do we configure short and long control symbols in K2K DSP

Best Regards

LN