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CCS/TDA3: Deep learning examples deploying, can't start sample projects

Part Number: TDA3

Tool/software: Code Composer Studio

We are trying to deploy TI DL system and having several issues.

  1. During c_intrinsics_host_port compilation (by the way we couldn’t find info on it in the user guide) we encountered a problem during LINK process.
C:\Program Files (x86)\Windows Kits\10\include\10.0.10240.0\ucrt\stdlib.h(305): error C2732: linkage specification contradicts earlier specification for '_ti_rotl'
C:\Program Files (x86)\Windows Kits\10\include\10.0.10240.0\ucrt\stdlib.h(302): note: see declaration of '_ti_rotl'

This can be avoided by CFLAGS+= -U_MSC_VER in algo make file, but we are not sure of this is a right solution.

  1. Net stat update option doesn’t change the file. The with_stat file remained the same as without. (Examples are in attachments).
  2. Work results of emulator and tda3xx debug application are different. In this same example emulator returns some result (together with trace dump), but tda3xx app creates an empty file.
  3. outDataQ  = (((inDataQ * weightsQ) + outPutShift/2) / outPutShift); (line 2437 ti_dl\algo\src\tidl_conv2d_base.c) in our example gives a division by zero error, while in tda mode
  4. int8_t *writePtr = (int8_t *)malloc(n*width*height); ti_dl\test\src\tidl_tb.c returns NULL

When we are using your samples both applications work adequately, so we think there might be some rules, that were not mentioned in the user guide

And one more question about CaffeImport:

What is this special argument for quantization. How can you specify it manually (option 10).  Are there any restrictions on Caffe files (are the ones we are using correct?) and if not could you please provide an example caffe files.

  • Hi Vladimir,

    I have forwarded your question to an expert.

    Regards,
    Yordan
  • Hello Mr. Vladimir Aparin,
    Since the query is for the software which is not publically released, can you please post in private forum mentioned below
    e2eprivate.ti.com/.../309.aspx

    Thanks,
    with Regards,
    Pramod
  • Hello Pramod,

    I can't access this forum. Invitation link are not active.
    Can you send me it again through private message?
  • For [1 and 2] 

    We have recently made release of version 00.007 TIDL. We have few modification in the make rules, and we do not have the _MSC_VER defined. I hope this issue is not present in this release. Please let us know, if you still observe this issue.

    For [3]

    Please run the examples present in the config folder and make sure your output matches with expected results in the reference folder. In the 00.007 release we have 3 examples ( Jseg21 Net, Squeezenet 1.1 and googleNet/InceptionNetV1). Please validate you environment with these examples in both host emulation mode and target. Since, the file I/O is slow in target, we disable trace file I/O. Only writes the final output.

    For [4]

    We identified this bug and fixed in the latest release. Please refer the releases notes

    For [5] We have limited external memory in with the current GEL configuration. If your Net requires more memory, then you may face this allocation issue. We have validated 3 networks with the test application that we provide in our release package. We are also working on memory foot print optimization, it will be available in next release.

    [ For CaffeImport ] You can use the SqueezeNet_v1.1 caffe files as example. Find the same in below git link. I have also attached  deploy prototxtt file for the same here.

    github.com/.../SqueezeNet_v1.1

    Deploy prototxt 

    8484.deploy.prototxt.txt

    Thanks and Regards,

    Kumar.