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AM5728: UART FIFO and shift register empty interrupt in DMA mode

John D97
Intellectual 540 points

Part Number: AM5728

I am sending some data over UART via EDMA. And I am getting an EDMA transmission complete interrupt when all data is fetched and placed onto UART FIFO. But we are using RS-485 and we need to start listening for the response and we must toggle the direction pin only after the last byte is transmitted, not when all data is placed into FIFO.

I know that this is doable if we weren't using EDMA, but directly write to FIFO instead (TX_EMPTY_CTL_IT bit in UART_SCR register), but is there a way to achieve the same result with EDMA?

  • 0
    TI__Guru**** 393215 points
    Yes, TX_EMPTY_CTL_IT = 1 should enable the THR interrupt to be generated when TX FIFO and TX shift register are empty.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 540 points
    Doesn't seem to work for me. What happens:
    Once I enable this interrupt, it immediately fires off, apparently because FIFO and shift register are empty. Datasheet says that in order to reset this interrupt, I have to "Write to the UART_THR until the interrupt condition disappears". And it's not like one would expect that you write one byte to UART_THR and interrupt is reset. My counter says that interrupt disappears only after 85 writes to UART_THR. But even it works only when I write to UART_THR manually. If EDMA writes to it, the interrupt is still considered pending and the new one does not fire off even after EDMA is done and all bytes are physically transmitted. Maybe that's because my EDMA transmission is less than 85 bytes.
    And artificial bytes, which I write to UART_THR, are transmitted and they litter the line.

    Seems like I have to implement it by FIFO without EDMA?