Hi,
I am using 1Gb DDR3 IC in DDR3A and another 1Gb DDR3 in DDR3B controller.
Please let me know whether these two controllers can be accessed at a time by any of the cores or peripherals ?
Thanks & Regards,
Madhu Sharma K
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Hi,
I am using 1Gb DDR3 IC in DDR3A and another 1Gb DDR3 in DDR3B controller.
Please let me know whether these two controllers can be accessed at a time by any of the cores or peripherals ?
Thanks & Regards,
Madhu Sharma K
Hi Madhu,
See 1.6 Functional Block Diagram from the device Data Manual.
One of the DDR controllers (DDR3A) is available for direct access from the ARM CorePac & DSP CorePack through the MSMC.
The other DDR (DDR3B) is available to the corepacks & the device peripherals through the TeraNet chip interconnection.
Best Regards,
Yordan