Failed to Load DSP server on DM6467, status=[0x80008017]

longxiao zhang

I've developed a codec and integrated it into a DSP server on DM6467. It works well until I place a part of my codes on L2 instead of DDR2.

Then, it failed to Load DSP server on ARM926, and returns:

@0,788,701us: [+0 T:0x40969490] OP - Processor_create_d> Enter(proc=0x5db18)
@0,788,778us: [+2 T:0x40969490] OP - Processor_create_d> Initializing DSP PROC...
@0,788,860us: [+2 T:0x40969490] OP - Processor_create_d> Using DspLink config data for entry #0 [server 'DM6467.x64P']
@0,788,964us: [+2 T:0x40969490] OP - Processor_create_d> Adding DSP segment #0 to Link configuration: name='DDR2', startAddress=0x8fa00000, sizeInBytes=0x400000, shared=1, syncd=0
@0,789,074us: [+2 T:0x40969490] OP - Processor_create_d> Adding DSP segment #1 to Link configuration: name='DSPLINKMEM', startAddress=0x8fe00000, sizeInBytes=0x100000, shared=1, syncd=0
@0,789,181us: [+2 T:0x40969490] OP - Processor_create_d> Adding DSP segment #2 to Link configuration: name='RESET_VECTOR', startAddress=0x8ff00000, sizeInBytes=0x80, shared=1, syncd=0
@0,789,281us: [+2 T:0x40969490] OP - Processor_create_d> Adding DSP segment #3 to Link configuration: name='DDRALGHEAP', startAddress=0x8b500000, sizeInBytes=0x4500000, shared=0, syncd=0
@0,789,474us: [+2 T:0x40969490] OP - Processor_create_d> DOPOWERCONTROL was=0; now=0
@0,797,302us: [+2 T:0x40969490] OP - Processor_create_d> Attaching to DSP PROC...
@0,803,146us: [+2 T:0x40969490] OP - Processor_create_d> Opening MSGQ pool...
@0,803,692us: [+2 T:0x40969490] OP - Processor_create_d> Loading DM6467.x64P on DSP (1 args)...
@0,860,240us: [+2 T:0x40969490] OP - Processor_create_d> Starting DSP PROC...
@16,666,477us: [+7 T:0x40969490] OP - Processor_create_d> Loading and starting DSP server 'DM6467.x64P' FAILED, status=[0x80008017] (look for error code 'DSP_EBASE + 0x17' in dsplink*/packages/dsplink/gpp/inc/usr/errbase.h)
@16,666,626us: [+0 T:0x40969490] OP - Processor_delete_d> Enter (proc=0x5db18)
@16,666,716us: [+2 T:0x40969490] OP - Processor_delete_d> Closing remote transport...
@16,666,823us: [+6 T:0x40969490] OP - Processor_delete_d> Closing remote transport FAILED, status=0x80008000.
@16,666,912us: [+2 T:0x40969490] OP - Processor_delete_d> Stopping DSP...
@16,667,012us: [+6 T:0x40969490] OP - Processor_delete_d> Stopping DSP FAILED, status=0x80008000
@16,667,102us: [+2 T:0x40969490] OP - Processor_delete_d> Closing pool...
@16,667,613us: [+2 T:0x40969490] OP - Processor_delete_d> Detaching from DSP...
@16,674,256us: [+2 T:0x40969490] OP - Processor_delete_d> Destroying DSP... (object, that is)
@16,674,941us: [+0 T:0x40969490] OP - Processor_delete_d> return
@16,675,059us: [+2 T:0x40969490] OP - Processor_create_d> return (0)

I found 'DSP_EBASE + 0x17' is DSP_ETIMEOUT in errbase.h. It looks like my DSP server doesn't respond.

If I place those codes in DDR2, there's no such problem.

I also tried to place some datas, not codes, on L2, there's no problem too.

So, what problem could it be?

-----------------------------------------------------------------

Here is .tcf of DSP server:

var mem_ext = [
{
    comment:    "DDRALGHEAP: off-chip memory for dynamic algmem allocation",
    name:       "DDRALGHEAP",
    base:       0x8B500000,
    len:        0x04500000,
    space:      "code/data"
},
{
    comment:    "DDR2: off-chip memory for code and data",
    name:       "DDR2",
    base:       0x8FA00000,
    len:        0x00400000,
    space:      "code/data"
},
{
    comment:    "DSPLINK: off-chip memory for DSPLINK code and data",
    name:       "DSPLINKMEM",
    base:       0x8FE00000,
    len:        0x00100000,
    space:      "code/data"
},
{
    comment:    "RESET_VECTOR: off-chip memory for the reset vector table",
    name:       "RESET_VECTOR",
    base:       0x8FF00000,
    len:        0x00000080,
    space:      "code/data"
},
];

var device_regs = {
    l1PMode: "32k",
    l1DMode: "32k",
    l2Mode: "64k"
};

var params = {
    clockRate: 594,
    catalogName: "ti.catalog.c6000",
    deviceName: "DM6467",
    regs: device_regs,
    mem: mem_ext
};

/*
* Customize generic platform with parameters specified above.
*/
utils.loadPlatform("ti.platforms.generic", params);

/* ===========================================================================
* Enable heaps and tasks
* ===========================================================================
*/
bios.enableMemoryHeaps(prog);
bios.enableTskManager(prog);

/* ===========================================================================
* Create heaps in memory segments that are to have heap
* ===========================================================================
*/
bios.DDR2.createHeap = true;
bios.DDR2.heapSize = 0x00040000; // 256K

bios.DDRALGHEAP.createHeap = true;
bios.DDRALGHEAP.heapSize = bios.DDRALGHEAP.len;

/* ===========================================================================
* GBL
* ===========================================================================
*/
prog.module("GBL").ENABLEALLTRC = false;
prog.module("GBL").PROCID = 0;

prog.module("GBL").C64PLUSCONFIGURE   = true ;
prog.module("GBL").C64PLUSL2CFG       = "64k" ;
prog.module("GBL").C64PLUSL1DCFG      = "32k" ;
prog.module("GBL").C64PLUSL1PCFG      = "32k" ;
prog.module("GBL").C64PLUSMAR128to159 = 0x0000ffff;

/* ===========================================================================
* HWI
* ===========================================================================
*/
bios.HWI_INT4.interruptSelectNumber = 16
bios.HWI_INT5.interruptSelectNumber = 17

/* ===========================================================================
* MEM
* ===========================================================================
*/
prog.module("MEM").STACKSIZE = 0x1000 ;
prog.module("TSK").STACKSIZE = 0x1000 ;

/* ===========================================================================
* Global Settings
* ===========================================================================
*/
prog.module("MEM").ARGSSIZE = 200;

/* ===========================================================================
* Enable MSGQ and POOL Managers
* ===========================================================================
*/
bios.MSGQ.ENABLEMSGQ = true;
bios.POOL.ENABLEPOOL = true;

/* ===========================================================================
* Set all code and data sections to use DDR
* ===========================================================================
*/
bios.setMemCodeSections (prog, bios.DDR2) ;
bios.setMemDataNoHeapSections (prog, bios.DDR2) ;
bios.setMemDataHeapSections (prog, bios.DDRALGHEAP) ;

/* ===========================================================================
* MEM : Global
* ===========================================================================
*/
prog.module("MEM").BIOSOBJSEG = bios.DDRALGHEAP;
prog.module("MEM").MALLOCSEG = bios.DDRALGHEAP;

/* ===========================================================================
* TSK : Global
* ===========================================================================
*/
prog.module("TSK").STACKSEG = bios.DDRALGHEAP ;

bios.TSK.instance("TSK_idle").stackSize = 0x1000;

//Fix for clock
prog.module("CLK").SPECIFYRATE = true;
prog.module("CLK").INPUTCLK = 148.5;

/* ===========================================================================
* Generate configuration files...
* ===========================================================================
*/
if (config.hasReportedError == false) {

bios.MEM.instance("IRAM").createHeap = 1;
bios.MEM.instance("IRAM").heapSize = 0x00008000;
bios.MEM.instance("IRAM").enableHeapLabel = 1;
bios.MEM.instance("IRAM").heapLabel = prog.extern("IRAM_HEAP", "asm");
bios.MEM.instance("IRAM").space = "code/data";
// !GRAPHICAL_CONFIG_TOOL_SCRIPT_INSERT_POINT!

prog.gen();
}

.cmd of DSP server:

SECTIONS
{
.intCode > IRAM
.csl_vect > DDR2
}

over 15 years ago

0 AC2150 over 15 years ago

TI__Intellectual 2605 points

hello,

This might help

http://tiexpressdsp.com/index.php/Configuring_Codec_Engine_in_Arm_apps_with_createFromServer#Adding_a_memory_segment_when_using_createFromServer.28.29_.28for_advanced_users.29

Cheers, Alan

0 longxiao zhang over 15 years ago

Intellectual 500 points

Thanks Alan:

I found some very useful words in that article:

Note for CE 2.10 users: Currently there is a bug where customized internal memory segments to the DSP are not automatically added by createFromServer as in the procedure above. These memory segments would need to be added manually in the application's cfg file, immediately after the call to createFromServer(). E.g.:

var Engine = xdc.useModule('ti.sdo.ce.Engine');
var demoEngine = Engine.createFromServer(...);
/*
* Add an internal memory segment at address 0x11818000 of size 0x10000. Must match .tcf file
* of DSP server
*/
demoengine.armDspLinkConfig.memTable[ "IRAM" ] = {addr: 0x11818000, size: 0x10000, type: "other"}

I thought maybe my codes in L2 is not loaded by CE. Then I add a memTab to my application's .cfg like above. And this time, the appliction prints out following info:

Modules linked in: dsplinkk cmemk
CPU: 0
PC is at memcpy+0xfc/0x330
LR is at 0xf7
pc : [<c01a82bc>] lr : [<000000f7>] Tainted: GF
sp : c4dadd14 ip : 00000001 fp : c4dadd2c
r10: bf022bf0 r9 : 00000000 r8 : 11820000
r7 : 00000000 r6 : 000012c0 r5 : 00000003 r4 : 00000003
r3 : 00000001 r2 : 000012bb r1 : c8108001 r0 : ffffffff
Flags: nzCv IRQs on FIQs on Mode SVC_32 Segment user
Control: 5317F
Table: 84CEC000 DAC: 00000015
Process video_read_enco (pid: 643, stack limit = 0xc4dac258)
Stack: (0xc4dadd14 to 0xc4dae000)
dd00: ffffffff 00000003 bf00b728
dd20: c4dadd4c c4dadd30 bf00e4b0 bf00b728 000012c0 c8108000 bf00cc9c 00000000
dd40: c4dadd7c c4dadd50 bf01395c bf00e478 c8108000 00000014 00008000 000012c0
dd60: c80b2000 c4dade18 00000004 c4dade80 c4dade6c c4dadd80 bf016ba0 bf0138f8
dd80: c8108000 c0088880 c4dadda4 00000000 c00742e8 bec75864 00000001 00000000
dda0: 00000034 8fafe860 c4daddfc 6f69622e 00000073 8faf8000 8faf8000 00006320
ddc0: 000c2a26 00000000 00000000 00000000 00000000 00000520 00000000 00002c2e
dde0: c4dade34 00000000 00000037 11820000 11820000 000012c0 000c1526 00000000
de00: 00000000 00000000 00000000 00000520 00000000 bf020001 c8108000 622e625c
de20: 00736f69 00000000 37000000 00000000 00000000 00000000 c80b8033 00000001
de40: bf021578 00008000 00000000 c8018000 0003625c 00000001 c4dac000 bec75864
de60: c4dadec4 c4dade70 bf0095b4 bf0165f4 bf021584 c4dadeb8 00000002 bf021294
de80: c80b2000 c4dade90 00000003 00000001 bf0138e8 bf0138b0 bf021294 bf021378
dea0: 00006c05 40968d74 00006c05 c0526480 00000009 00000000 c4dadf24 c4dadec8
dec0: bf008578 bf009478 c4d7e000 00000001 c4dadf2c c4dadee0 c009c1ac c00ab03c
dee0: c008070c c0079aec c4dadf30 c52450e0 000008ad c4c39850 00008000 00000000
df00: 0003625c 00000001 bec75864 2f008000 c0526480 40968d74 c4dadf44 c4dadf28
df20: c00a2710 bf00809c 00000060 c0526480 00000009 40968d74 c4dadf74 c4dadf48
df40: c00a29f0 c00a26a4 00000000 26259fff 00000060 00000000 40968d74 00006c05
df60: 00000009 c4dac000 c4dadfa4 c4dadf78 c00a2acc c00a273c 0000012a 00000001
df80: c4dac000 00000281 0005c510 0005c560 00000036 c0030f88 00000000 c4dadfa8
dfa0: c0030f58 c00a2a28 00000281 0005c510 00000009 00006c05 40968d74 00000009
dfc0: 00000281 0005c510 0005c560 00000036 00000064 00000005 000470fc 40968d5c
dfe0: 0005dc24 40968c88 000267ec 400ff27c 20000010 00000009 00007469 8fb47230
Backtrace:
[<bf00b718>] (MEM_Copy+0x0/0x18 [dsplinkk]) from [<bf00e4b0>] (DSP_write+0x48/0x54 [dsplinkk])
[<bf00e468>] (DSP_write+0x0/0x54 [dsplinkk]) from [<bf01395c>] (LDRV_PROC_write+0x74/0xbc [dsplinkk])
r4 = 00000000
[<bf0138e8>] (LDRV_PROC_write+0x0/0xbc [dsplinkk]) from [<bf016ba0>] (COFF_load+0x5bc/0x670 [dsplinkk])
[<bf0165e4>] (COFF_load+0x0/0x670 [dsplinkk]) from [<bf0095b4>] (PMGR_PROC_load+0x14c/0x24c [dsplinkk])
[<bf009468>] (PMGR_PROC_load+0x0/0x24c [dsplinkk]) from [<bf008578>] (DRV_Ioctl+0x4ec/0x9a0 [dsplinkk])
[<bf00808c>] (DRV_Ioctl+0x0/0x9a0 [dsplinkk]) from [<c00a2710>] (do_ioctl+0x7c/0x98)
r5 = 40968D74 r4 = C0526480
[<c00a2694>] (do_ioctl+0x0/0x98) from [<c00a29f0>] (vfs_ioctl+0x2c4/0x2ec)
r6 = 40968D74 r5 = 00000009 r4 = C0526480
[<c00a272c>] (vfs_ioctl+0x0/0x2ec) from [<c00a2acc>] (sys_ioctl+0xb4/0xe8)
r9 = C4DAC000 r8 = 00000009 r6 = 00006C05 r5 = 40968D74
r4 = 00000000
[<c00a2a18>] (sys_ioctl+0x0/0xe8) from [<c0030f58>] (__sys_trace_return+0x0/0x28)
r8 = C0030F88 r7 = 00000036 r6 = 0005C560 r5 = 0005C510
r4 = 00000281
Code: e4d1e001 c4c03001 a4c04001 e052200c (e4c0e001)
0]

It looks like my application get crashed this time.

0 SEED International over 15 years ago in reply to longxiao zhang

Prodigy 10 points

Glad your problem is solved.

Processors

Processors forum

Failed to Load DSP server on DM6467, status=[0x80008017]

Here is .tcf of DSP server:

.cmd of DSP server: