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C6457 SYSCLK6 (CHIP_CLKS) settings when in SPI master

Rob Beck
Intellectual 970 points

When I set up the PLL I have set the /y divider to /10 so on 1GHz C6457 I should have a 100MHz SYSCLK6.

However, when I read back the divider (when the SPI has started) in order to see the status of the PLL I see a divider of /6 for SYSCLK6 which comes out to 166MHz, which according to the manual violates the maximum 100MHz.

I am running a C6457 McBSP in SPI (clock-stop) master mode.

Is the SYSCLK6 (CHIP_CLKS or mcbsp_clks) divider setting slaved to SYSCLK5 which on the C6457 always uses a /6 divider when the C6457 is operating McBSP in SPI master mode?

  • 0
    TI__Guru* 84110 points

    Rob Beck said:
    Is the SYSCLK6 (CHIP_CLKS or mcbsp_clks) divider setting slaved to SYSCLK5 which on the C6457 always uses a /6 divider when the C6457 is operating McBSP in SPI master mode?

    SYSCLK6 is programmable and is not slaved to any of the other similar dividers.

    When you set up the PLL with /y = /10, can you read back the value and confirm that the /10 ratio was correctly programmed? When do you do this setup?