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TMS320DM8148: DM8148 OPP 100 Capabilities

Part Number: TMS320DM8148

Hi

My use case is to encode a 1080p30 and a PAL video simultaneously. We want to use DM8148 with DVR RDK. DM8148 is available in 3 variants as OPP100, OPP120, OPP160. Is OPP100 sufficient for my use case ??

Regards,

Pranay Kumar

  • Hi Kashetty,

    I think OPP100 should be enough for your use case. See the below wiki pages:

    processors.wiki.ti.com/.../TI81XX_PSP_04.04.00.02_Feature_Performance_Guide
    processors.wiki.ti.com/.../TI811X-HDVPSS-01.00.01.44_Feature_Performance_Guide

    The performance test is run at OPP100, see the default clock rates:

    processors.wiki.ti.com/.../TI81XX_PSP_04.04.00.02_Feature_Performance_Guide

    Cortex-A8 ARM at 600MHz:
    ./osc0_clkin_ck/arm_dpll_clkin_ck/arm_dpll_ck/mpu_ck/rate ==> 600000000

    SGX graphics at 200MHz:
    ./osc0_clkin_ck/sgx_dpll_ck/rate ==> 20000000

    HDVPSS at 200MHz:
    ./osc0_clkin_ck/hdvpss_dpll_ck/hdvpss_proc_fck/rate ==> 20000000
    ./osc0_clkin_ck/video1_dpll_clkin_ck/video1_dpll_ck/hd_venc_g_ck/rate ==> 20000000
    ./osc0_clkin_ck/hdmi_dpll_clkin_ck/hdmi_dpll_ck/hdmi_dpll_muxout_ck/hd_venc_d_ck/rate ==> 20000000

    DDR3 at 400MHz:
    ./osc0_clkin_ck/ddr_dpll_clkin_ck/ddr_dpll_ck/ddr0_phy_fck/rate ==> 400000000

    ISS at 400MHz:
    ./osc0_clkin_ck/iss_dpll_ck/iss_ick/rate ==> 400000000

    DSP at 500MHz:
    ./osc0_clkin_ck/dsp_dpll_ck/gem_fck/rate ==> 500000000

    Seems that only HDVICP2 is used at OPP120 (306MHz):
    ./osc0_clkin_ck/hdvicp_dpll_ck/sysclk3_ck/ivahd0_ck/rate ==> 306000000

    See also the below e2e thread:

    https://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/201966

    Regards,
    Pavel

  • Hi Pavel,

    Is there any Document or wiki which tells the video encode or decode capabilities of OPP100/120/166? Like which OPP supports which all formats and their combinations ?

    Regards,
    Pranay Kumar
  • Hi,

    I have a hardware with DM8148 Part No: TMS320DM8148CCYE1 which is of OPP166 . For our next project we require an industrial grade part which is available only with OPP100 .

    To test whether OPP100 is capable of our use case, I modified the frequency of HDVICP to 266 MHz(OPP 100) in our current project. I have not modified the frequencies of ARM, DDR and VPSS.

    I have modified the frequency in Encoder and found out no issues to encode a 1080p30 video.

    When I modified the frequency of HDVICP in decoder, it is able to decode the 1080p30 video but slowly the delay is getting accumulated. When I changed back the frequency of HDVICP the decoder(to 440 MHz) behaviour is proper. Our current links are

    ARM --> Decoder --> VPSS --> Scalar --> Display

    My questions are:
    1. Is there are any issues in my experiment ?
    2. Any idea why the delay is getting accumulated ??

    Regards,
    Pranay kumar
  • kashetty pranay kumar said:
    To test whether OPP100 is capable of our use case, I modified the frequency of HDVICP to 266 MHz(OPP 100) in our current project. I have not modified the frequencies of ARM, DDR and VPSS.

    Do you mean that you have HDVICP2 at OPP100, and ARM/DSP at OPP166? If yes, this is not supported combination, see DM814x datasheet, Table 7-5. Supported OPP Combinations

    kashetty pranay kumar said:
    When I changed back the frequency of HDVICP the decoder(to 440 MHz)

    For CYE1 device (TMS320DM8148CCYE1), HDVICP2 can run max at 410MHz for OPP166, see DM814x datasheet, Table 7-4. Device Operating Points (OPPs)

    kashetty pranay kumar said:
    1. Is there are any issues in my experiment ?

    The issues are commented above

    kashetty pranay kumar said:
    2. Any idea why the delay is getting accumulated ??

    Because of the slower HDVICP2 frequency, what else can be?

    Regards,
    Pavel