AM5728: QSPI maximum frequency

The Datasheet publishes the correct max QSPI frequency.  See “Table 7-46. Switching Characteristics for QSPI” in SPRS9543C.  (Note, the max freq for Mode 0 is 76.8 MHz  (1 / 13.02 ns), not 128 Mhz.)

“Table 33-17. ROM Code Default Clock Settings” in the TRM shows the settings for the internal QSPI_FCLK.  The qspi1_clk output is a divided version of the internal QSPI_FCLK clock.  See section “24.5.4.1.4  SPI Clock Generator” in the TRM for more details.  The actual qspi1_clk frequency used by the ROM is shown in Section “33.3.7.5  SPI/QSPI Flash Devices” of the TRM.  

Regards,

Melissa

Matusan,

I think that you are confusing the different device clock names associated with QSPI IP. Please refer to the clock tree tool for this device.
www.ti.com/.../CLOCKTREETOOL

Select the signal names that you want to view in the "Signal Name" tab and zoom into the see the clock structure. the selected signal will show up as dotted line in the tool.

The clock PER_QSPI_CLK is the one of PLL Source clock used for the QSPI module. QSPI_FCLK that is divided down from the PLL source to provide as input clock to the QSPI module. and the QSPI_FCLK gets further divided down in the IP to get to the QSPI output clock.

The output clock for QSPI IP on the device supports max freq of ~75 MHz as Melisssa has indicated. This refers to the output clock from the IP that is connected to the serial NOR flash devices. The ROM bootloader boot the device a 48 Mhz, application developers can go to higher frequency if required post boot.

Regards,
Rahul

Hi,

 

Thank you for your detailed explanation.

I really appreciate your help.

We can find "the clock PER_QSPI_CLK is the one of PLL Source clock of QSPI_GFCLK" in CCT-Tool. 

Best regards,