Part Number: AM3351
Good afternoon,
I'm using a custom AM3351 board with MMC0 SD card boot, and was originally using the boot sequence
MMC0 -> SPI0 -> UART0 -> USB0
I've seen changed my boot sequence as it sometimes failed to boot from MMC0 and would hang on USB0. My new boot sequence is XIP [MUX MODE2] -> UART0 -> EMAC1 -> MMC0. However, with the new boot sequence I'm not able to use GPIO2[22] and GPIO2[23]. It appears that the XIP boot is perhaps re-assigning these pins so that I'm no long able to toggle them as gpio-leds. I know that there is some overlap between these GPIO and XIP pins. I'm very much confused because in my device tree I'm setting them as outputs, active high, and enabled, but they are output low after boot. If I change the boot sequence to remove XIP boot, then it works perfectly.
Please let me know if you have any suggestions.
In my device tree
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&usb_hub_pins>;
reset_led {
label = "hub_reset";
gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
heartbeat_led {
label = "heartbeat";
gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
default-state = "on";
};
audio_codec_enable {
label = "audio_codec_enable";
gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
audio_amp_enable {
label = "audio_amp_enable";
gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
default-state = "off";
};
audio_gain_0 {
label = "audio_gain_0";
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
audio_gain_1 {
label = "audio_gain_1";
gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
fan_enable {
label = "fan_enable";
gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
battery_charge_enable {
label = "battery_charge_enable";
gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
battery_backup_enable {
label = "battery_backup_enable";
gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
gpio_pins: gpio_pins {
pinctrl-single,pins = <
0x88 ( PIN_INPUT | MUX_MODE7 ) /* (U17) gpmc_csn3.gpio2[0] */
0x8c ( PIN_INPUT | MUX_MODE7 ) /* (V16) gpmc_clk.gpio2[1] */
0x90 ( PIN_INPUT | MUX_MODE7 ) /* (V10) gpmc_advn_ale.gpio2[2] */
0x94 ( PIN_INPUT | MUX_MODE7 ) /* (W9) gpmc_oen_ren.gpio2[3] */
0x98 ( PIN_INPUT | MUX_MODE7 ) /* (U8) gpmc_wen.gpio2[4] */
0x9c ( PIN_INPUT | MUX_MODE7 ) /* (V8) gpmc_be0n_cle.gpio2[5] */
0xa0 ( PIN_INPUT | MUX_MODE7 ) /* (U1) lcd_data0.gpio2[6] */
0xa4 ( PIN_INPUT | MUX_MODE7 ) /* (U2) lcd_data1.gpio2[7] */
0xa8 ( PIN_INPUT | MUX_MODE7 ) /* (V1) lcd_data2.gpio2[8] */
0xac ( PIN_INPUT | MUX_MODE7 ) /* (V2) lcd_data3.gpio2[9] */
0xb0 ( PIN_INPUT | MUX_MODE7 ) /* (W2) lcd_data4.gpio2[10] */
0xb4 ( PIN_INPUT | MUX_MODE7 ) /* (W3) lcd_data5.gpio2[11] */
0xb8 ( PIN_INPUT | MUX_MODE7 ) /* (V3) lcd_data6.gpio2[12] */
0xbc ( PIN_INPUT | MUX_MODE7 ) /* (U3) lcd_data7.gpio2[13] */
0xc0 ( PIN_INPUT | MUX_MODE7 ) /* (V4) lcd_data8.gpio2[14] */
0xc4 ( PIN_INPUT | MUX_MODE7 ) /* (W4) lcd_data9.gpio2[15] */
0xc8 ( PIN_INPUT | MUX_MODE7 ) /* (U5) lcd_data10.gpio2[16] */
0xcc ( PIN_INPUT | MUX_MODE7 ) /* (V5) lcd_data11.gpio2[17] */
0x138 ( PIN_INPUT | MUX_MODE7 ) /* (N16) gmii1_rxd2.gpio2[19] */
0x13c ( PIN_INPUT | MUX_MODE7 ) /* (P19) gmii1_rxd1.gpio2[20] */
0xe0 ( PIN_OUTPUT | MUX_MODE7 ) /* (U7) lcd_vsync.gpio2[22] */
0xe4 ( PIN_OUTPUT | MUX_MODE7 ) /* (T7) lcd_hsync.gpio2[23] */
0xec ( PIN_INPUT | MUX_MODE7 ) /* (W7) lcd_ac_bias_en.gpio2[25] */
>;
};
