Hello,
I have found some inconsistencies in the documentation regarding the RMII_REFCLK pin and was hoping someone could shed some light on this for me.
In the datasheet, the pin is shown as an input (section 4.3.13) and as IOZ (Section 4.2). In the TRM, it is shown as an output (section 11.13.4.2.2) and as an input (Figure 11-904).
From the datasheet:
RMII_REFCLK pin is implemented as pad loopback inside the device — the output signal is looped back through the input buffer to serve as the internal reference signal. Series termination is required (as close as possible to device pin) to improve signal integrity of the clock input.
This, combined with the CFG registers associated with the pin, seems to indicate that the pin can be used in the following ways:
1. CLKOUT is driven with 50MHz signal. RMII_REFCLK and the PHY receive this clock signal, as shown in TRM Figure 11-904
2. CLKOUT is High Z and RMII_REFCLK is configured as a input.
In case 1, is it the case that the device pin associated with RMII_REFCLK would output the CLKOUT signal?
Is case 2 possible?
Thank you for your help,
Jeff
