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AM5726: PCIe config command response

shigehiro tsuda
Mastermind 9490 points
Part Number: AM5726


Hi,

The Configuration cycle is executed from the control(RC), but normal operation can not be confirmed.
The analyzer confirms the operation that the AM5726(EP) does not correctly respond to the Config command.

Is there a setting required for the AM5726 in order to respond normally to the Config command after the L0 state transition?
Or does register setting by software are unnecessary and can it respond with only hardware?

Best Regards,
Shigehiro Tsuda

  • 0
    TI__Guru**** 393215 points
    The PCIe experts have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    Mastermind 9490 points

    Hi Biser,

    Thank you for quick reply.
    Did you receive a response from the PCIe experts?
    Our customers seem to want to solve this problem as soon as possible.

    Best Regards,
    Shigehiro Tsuda

  • 0 in reply to shigehiro tsuda
    TI__Guru**** 393215 points
    This is 4-th of July week in the USA and a lot of people are out of office. They will post directly here when possible.
  • 0 in reply to Biser Gatchev-XID
    Mastermind 9490 points

    Hi Biser,

    Thank you for quick reply.
    I understand that people in the USA were out of office last week.

    Is there any update information from the PCIe experts?
    Our customers seem to want to solve this problem as soon as possible.

    Best Regards,
    Shigehiro Tsuda

  • 0 in reply to shigehiro tsuda
    TI__Guru* 95265 points
    Hi,

    Can you elaborate the HW and SW used for this question? What is the PCIE RC and what software runs on AM572x? It looks linking training succeeded and L0 is reached. What is the config command send to EP? Do you try to write into some register of EP side?

    Regards, Eric
  • 0 in reply to lding
    Mastermind 9490 points

    Hi Eric,

    Thank you for quick reply.

    The PCIE RC is the processor of other company.
    The OS use VxWorks, our customer is creating drivers based on the ti-processor-sdk-RTOS PCIe sample program.

    Configure read command is sent from the RC side to the EP side.
    At that time, CRS(Config Request Retry Status) is sent from EP side.

    Our customers do not seem to make the following settings before Link establishes.
    ① BAR(Inbound and Outbound) setting
    ② Setting of Device ID and Vendor ID

    Is the above setting necessary for the AM5726 to properly receive configure read command?

    Best Regards,
    Shigehiro Tsuda

  • 0 in reply to lding
    Mastermind 9490 points
    Hi Eric,

    Is there any update information?

    Best Regards,
    Shigehiro Tsuda
  • 0 in reply to shigehiro tsuda
    TI__Guru* 95265 points

    Hi,

    Sorry for the late response!

    1) It is still unclear the configuration read is BEFORE or AFTER link training? The initial post said "Is there a setting required for the AM5726 in order to respond normally to the Config command after the L0 state transition?". If you already reaches L0 state, the AM572x PCIE configuration space is memory-mapped into the RC side, they can be accessed through register read and write. Why you do another configuration read? Before link reaches L0 state, typically PCIE RC does the enumeartion process, it involves in configuration read, if you can reach L0 that means the configuration read is successful at that time. Then why it fails after reaching L0?

    2) Does the PCIE RC enmuration (like running some Linux/Windows operating system) or there is no enumeration process at all? You refer to our Processor SDK RTOS PCIE example, this code DOESN'T DO the enumeration, it is just set both ends individually and starts the link training process. The setting in BAR registers is different in two cases:

    A. in enumeration case, the EP side BAR register is only programed with BAR mask, it indicates how many memory space it asked from RC. The RC writes all ones to EP's BARs and reads back the device's requested memory size and allocate it from system resource, then writes the BAR address into it.

    B. In pure link training case (our RTOS example), the BAR is programed with bar mask and bar address to match between RC and EP, as there is no enumearuion process.

    Regarding the DEVID and VENDID, it is 0x8888104C by default after reset. You don't need to program it again unless you want to change it to some other value.

    In summary, if I assume your usage case: 1) RC does enumeartion 2) the configuration read is before reaching L0. Then you need to program BAR mask in the EP side, but DEVID/VENDID is not necessary.

    You may refer to  https://en.wikipedia.org/wiki/PCI_configuration_space if your question is the configuration read during bus enumeration? Or I understood your situation wrong?

    Regards, Eric

  • 0 in reply to lding
    Mastermind 9490 points
    Hi Eric,

    Thank you for quick reply and detailed explain.
    They are using RC side processors Vxworks.
    Perhaps VxWorks is also a driver that requires enumaration like Windows and Linux .
    Therefore, it seems that it does not work on ti-processor-sdk-RTOS based source.
    When BAR MASK on the EP side is set, I will check what happens to the protocol analyzer.
    I understood that setting of DEVID / VENDID is not necessary.

    Best Regards,
    Shigehiro Tsuda
  • 0 in reply to lding
    Mastermind 9490 points
    Hi Eric,

    I have been informed that our customer has successfully started the read configuration command.
    Based on your advice, it seems that they found a solution to this problem.
    I appreciate your response.

    Best Regards,
    Shigehiro Tsuda