Part Number: AM5708
Other Parts Discussed in Thread: AM5728
Hi,
During the Board Bringup phase for our design based on the AM5708, we started with bringup the bootloaders (have ti-u-boot code running which boots on the BBX15 (AM5728)).
We created our own board file and mux, added the emif data and all board specifics to the code and built it for our own design (Having the Alliance DDR3 memory).
We use 2x 2GigaBit (265 MB) memories multiplexed (one chip get's data lines 0-15, the other one has data lines 16-31 and they both share the address lines.
SPL (MLO or second stage bootloader) starts and reaches up to console access (succesfully initializing sdram -> ddr3) and then tries to boot u-boot. There we noticed some inconsistencies in the DDR3 memory.
After investigating and creating (simplified) RAM tests for DDR3, we noticed that the DDR3 memory is not 'reliable'. On one board we seem to be able to use only the upper 16 bits of each 32 bit value, (where the 16 LSB's are mostly the same (0xC8FE) they sometimes change their value with a few bits. (Writing patterns over memory addresses result in such tables :
1st Board:
Writing 0xEFFFFFFF - Reading 0xEFFFC8FE
Writing 0xFFFEFFFF - Reading 0xFFFEC8FE
Writing 0x000000001 - Reading 0x0000C8FE
2nd Board:
Writing 0xEFFFFFFF - Reading 0xEFFFFFFF (Correct)
Writing 0xFFFEFFFF - Reading 0xFFFEFFFE (1 Bit Off)
Writing 0x000000001 - Reading 0x000000000 (1 Bit Off)
This seems the 2nd board is behaving "Better" but we cannot get our finger around what / why.
Actions that we have taken so far:
- Verify the timings (EMIF registers) to the timings from the TI input (Excel sheets /Tools) -> OK
- Verify Clocks with scope -> OK
- Lower Speed (Set timing lower to 400MHz) and verify with Scope -> OK.
- Monitor voltages (From what we can meassure) -> OK.
- XRay in Factory to verify solderings on DDR3 RAM -> OK (No abnormalities seen).
- Update: Verify with JTAG and GEL files that we can access the RAM using debugger (Successfull: This revealed that board 1 had a fried RAM, so therefore ignorable, 2nd Board was debuggable using JTAG and the DDR3 ram was tested using a (simple) memtest routine over the entire RAM. (Write entire ram to pattern, read it back).
Next we tried to print the settings for all Emif Registers in both SPL and compare them to the settings in the working JTAG example. See attached file for diff.
Question:
- What other paths can we investigate with these problems?
- Any steps that we missed?
- Issues that you are aware of?
- Open doors to check?
