RTOS/AM3352: L1 cache questions

Kummi

Part Number: AM3352

Tool/software: TI-RTOS

Hi,

If we want to Enable the L1 cache parity, should it be enabled
before Cache invalidation or after Cache invalidation?

Couldn't find the procedure to enable L1 cache parity in TI's or ARM's manual.

Best Regards
Kummi

over 8 years ago

0 Kummi over 8 years ago

Mastermind 6220 points

Part Number: AM3352

Tool/software: TI-RTOS

Hi,

The "L1 data cache hardware alias support" seems to be enabled by default.
Please let me know if there is more details on the cache hardware alias,
like disadvantages of not using this feature. Should we use it as per default setting?

Best Regards
Kummi

0 Biser Gatchev-XID over 8 years ago in reply to Kummi

TI__Guru**** 393215 points

The RTOS team have been notified. They will respond here.

0 Rahul Prabhu over 8 years ago

TI__Guru** 116770 points

you need to post this question on ARM community forums for the experts to respond to this question. Conventional wisdom would indicate that parity should be enabled after the invalidation so that parity is enabled after the refresh to the most current state but the ARM experts will be able to confirm this. We don`t enable parity bit in the RTOS software

0 Kummi over 8 years ago in reply to Rahul Prabhu

Mastermind 6220 points

Hi Rahul,

Thank you.

Could you please let me know if there is any info on the second question
"L1 data cache hardware alias support.."

Actually, I have posted questions on the ARM forum but didn't get the proper response there.

0 Lalindra Jayatilleke over 8 years ago in reply to Kummi

TI__Mastermind 30365 points

Kummi,

We are unsure on any performance difference of using or not using the ARM L1 data cache hardware alias support, hence the reason for asking the question on the ARM forums for a better response.

Let me check with some folks internally as well and will post back here if I have any feedback.

Lali

Processors

Processors forum

RTOS/AM3352: L1 cache questions