a question about the role of osd clock

feng said:

I am not clear about the role of osd clock. does osd clock refer to the time when osd fetch data from ddr?

The OSD clock is the rate at which the OSD peripheral within the device is driven, for most devices (such as DM6446) this should always be 13.5 MHz when using NTSC/PAL output so that it operates at half the rate of the VENC. This is related to the rate that the OSD collects data from DDR, though there is more to the data collection than the clock.

feng said:

I do a simple test: If I set venc_osdclk0 to 0x00 and set venc_osdclk1 to 0x01 while the default value is 0x01 and 0x02 in PAL/NTSC mode, this means that I increase the osd clock to  27MHZ from 13.5M, then I just  see a part of picture at the left, and the right part is blank....

I suspect this is due to some timing violation in the VPBE, as mentioned above when performing NTSC/PAL interlaced output the OSD must be clocked at half the VENC speed.

thanks , thompson. VPBE spec say that NTSC/PAL osd clock should be 13.5Mhz while if output in digital format it's should be 27Mhz. and I don't know why shoud do like this....... , and if I want to enable analog output and digital output simulatenously , which clock should I set to osd? thanks

As it shows in Table 57 of the VPBE User's Guide, the OSD clock must be set to 13.5 Mhz for NTSC/PAL formats.  I'm not sure where you found that the OSD clock must be set to 27 MHz, unless you are referring to HDTV/EDTV formats.  In these cases, the OSD clock must be 27 MHz because the video rate is doubled.

It is possible to enable both analog and digital outputs, but they would have to use the same timing.  In this case, the OSD clock would need to be 13.5 MHz and the digital output would have to be interlaced, but from your description, it doesn't sound like that's what you want to do.

hi, david

     In VPBE user guide section 4.5.2 , it require to clear OCPW bit to 0 and set the OCPT bit to 1 for progressive scan ouput. So I just guess for a digital ouput , if venc clock is 27Mhz, then OSD clock should be 27M hz. sorry for my misunderstanding.

  I do a simple test for analog and digital output simultaneously 

                   1) boot up from PAL standard tv mode 

                   2) after the system boot up and PAL TV display properly . then  enable VCLK output (set VIDCTL to 0x2001)

                   3) enable LCD_OE by setting LCDOUT to 0x03

                  4) enable horizontal/vertical sync output by setting SYNCCTL to 0x4003.

                  5) set digital output mode to PRGB by setting VMOD to 0x2043

                 6) set DCLKCTL to 0x801, set DCLKPTN0 to 0x03

                 7) set OSDCLK0 to 0x0 and OSDCLK to 0x1

         after setting HSTART/HVALID, VSTART/VVALID register, then I can oberserve that vclk pin output 27M clock, h/v sync pin output sync signal, R3/G3/B3/R4/G4/B4/R5/G5/B5/R6/G6/B6 output data, but seems there are nothing ouput at pin R0/G0/B0/R1/G1/B1/R2/B2/G2. it's stange.......

     and I also doubt about how to set RGB666 or RGB888? after reading vpbe spec, I just found the vmod register can set PRGB output, I also set PINMUX0 to 0x0180001f. Since I have set PINMUX0 bit 23 , so the pinmux is set to RGB888 mode, and does this means the digital data output format is RGB888 or just the output pin will work at RGB888? and which document describe PINMUX0 in details? If enable RGB888 , why does R/G/B/0/1/2 output nothing?

    thanks

by setting VIDCTL to 0x2000, then R/G/B/0/1/2 output data properly. thanks