Hi all,
As the link shows,
e2e.ti.com/.../2232107
I am struggling with bringing secondary arm core up on 66AK2L06.
I review boot-monitor commit log on git.ti.com and find out that TI made change about arm boot magic address.
Currently the arm boot magic address and entry setting in boot-monitor is show as follow:
#define CORE_N_BASE_ADDR_ARM0 0x02501040
unsigned int *addr = (unsigned int *)CORE_N_BASE_ADDR_ARM0;
for (i = 1; i < ARM_CLUSTER_NUM_CPUS; i++) {
addr[i * 2] = (unsigned int )_skern_123_init;
}
But the secondary arm core doesn't execute instruction at all on my board.
I have added debug function in skernel.S to check if secondary arm core could execute instruction by putting debug info on UART0 with assembly code.
It's like this:
.global _skern_123_init
_skern_123_init:
@
@ we came here after RBL fast boot
@ we don't need to save SP and other registers
@ we just install monitor vectors and stack for us
@
b __debug_test
If I revert the arm boot magic address to old one as follows:
#define CORE_N_BASE_ADDR_ARM0 0x0c1d2500
unsigned int *addr = (unsigned int *)CORE_N_BASE_ADDR_ARM0;
for (i = 1; i < ARM_CLUSTER_NUM_CPUS; i++) {
addr[i] = (unsigned int )_skern_123_init;
}
The secondary arm core can execute my debug code and put debug information on UART0.
But it hangs up after executing mcr instruction as follows:
.global _skern_123_init
_skern_123_init:
@
@ we came here after RBL fast boot
@ we don't need to save SP and other registers
@ we just install monitor vectors and stack for us
@
@b __debug_test
mrs r8, cpsr
bic r8, r8, #0x1f
orr r8, r8, #0x16
msr cpsr_c, r8
@b __debug_test
ldr r1, =monitor_vectors
@b __debug_test
mcr p15, #0, r1, c12, c0, #1 @secondary arm hangs when execute this instruction
b __debug_test @no reach here
mrc p15, #0, r0, c0, c0, #5
and r0, r0, #3
@b __debug_test @no reach here
It's so fuzzy. There isn't any document which illustrate the arm boot magic address on 66AK2L06.
What should I do on this issue?
