RTOS/K2GICE: PCIe's LTSSM_STATE does not change. Just fixed to DETECT_ACT(0x01)

Hi,

I've notified the RTOS team. Their feedback will be posted here.

Best Regards,
Yordan

Hi,

I didn't test K2G ICE EVM but I tested K2G GP EVM in the past. The PCIE sub-system is the same. Let me know how you tested? Why you need MLO? Is your K2G PCIE RC or EP? What is the other side of K2G EVM via PCIE? How they are connected?

Please look at processors.wiki.ti.com/.../Processor_SDK_RTOS_PCIe how we tested it.

Regards, Eric

Hi Eric,

Thanks for reply.

I tested with host Windows 10 PC and I also tested with CCS6 project but it was same result.
Naturally, it is used as an endpoint.
MLO is not absolutely necessary.

Did K2GICE never test as an PCIe EP?

Regards,
Jo

Eric,

My K2GICE's cpu part name is XD1030K011ZBB60.

Is it same with X66AK2G02ZBB60? Or any different?

Regards,

Jo

Hi Jo,

Here is what I found on K2G ICE EVM HW user guide,

2.3 Clocking

The K2G ICE EVM derives all internal clocks, with the exception of the PCIE_CLK, from a single clock

input. That clock input can be either the internal oscillator using crystal Y1, or an external clock generator

connected to SYS_CLK_P/N. The PCIE clock is only present if the K2G EVM is inserted into a PCIE

backplane.

2.11 PCIE Edge Connector

The K2G ICE includes a PCIE x1 edge connector as defined by the PCI Express Electromechanical

Specification, Rev 2.0. While the edge connector and the board thickness are compatible with that

standard, the K2G ICE was not designed to meet all the requirements for the Electromechanical

specification, and is not designed to fit into a standard PC chassis. No I/O bracket is available, and the

EVM is not compliant with the PCB form factor or component height restrictions.

Although the K2G can be configured as a PCIE root-complex or endpoint, the K2G ICE only supports

PCIE endpoint operations. The PCIE reference clock is only provided by the PCIE connector. No

accesses to the PCIE portion of the K2G SOC should be performed unless a PCIE reference clock is

present on the PCIE edge connector.

3.3.5 PCIe Edge Connector (J7)

The K2G ICE includes a x1 PCI Express endpoint connector capable of insertion into a PCI Express

backplane connector. The K2G ICE is not compliant with the PCI Express Card Electromechanical

Specification and is not designed to be inserted into a personal computer.

The K2G ICE does not include an onboard 100-MHz PCIe reference clock. If the PCIe interface is active,

a 100-MHz clock must be present on pins A13 and A14 for proper operation. While the K2G SoC can

support both root complex and endpoint operation, this EVM is only designed to act as an endpoint.

The PCIe backplane specification includes +12 V and +3.3 V to power cards inserted into the connector.

The +12 V from the PCIe backplane can be used to power the K2G ICE. If +12 V is present on the

backplane connector, there is no need to connect a power source to the DC jack (J6). If both voltage

sources are present, the power supply uses the higher of the two voltages.

So this EVM is designed as an PCIE EP and to receive PCIE 100MHz reference clock and power supply from PCIEx1 edge connector, but it is not designed to be inserted into a PC. I doubt we have any test case like yours. I will find out how we tested it.

Regards, Eric

 

Thanks Eric.

But I can't understand that this EVM is designed to act as an endpoint but is not designed to be inserted into a PC.
Has the manufacturer not tested PCIe while developing this board?

Regards,
Jo