why does pal_composite_config set YCCCTL's R656 bit?

feng said:

In the davinci frame buffer driver, if enable NTSC/PAL output, then always set register YCCCTL  bit0, it means enalbe REC656 mode. why?

I suspect the display driver just happens to set the bit, for analog display output the REC656 bit is not necessary so it should not impact the analog output.

feng said:

what's the meaning of setting this bit for DM6441?

Setting the REC656 bit will allow the digital bus to output a bt.656 standard stream, however there are additional settings that would have to be handled to actually have digital output, this is just one specifically for bt.656.

feng said:

does it mean that the digital output will output rec656/ycc8 format signal and data when the dac output cvbs signal?

If the digital output was enabled than yes it should output a bt.656 standard stream.

thanks for your explaintion.

and  can I enable YCC16 or PRGB(RGB666/RGB888) format output when output standard timing(PAL/NTSC) analog output?

Bernie Thompson said:

Setting the REC656 bit will allow the digital bus to output a bt.656 standard stream, however there are additional settings that would have to be handled to actually have digital output, this is just one specifically for bt.656.

Hi, thompson

     I do a simple test:

                   1) boot up from PAL standard tv mode 

                   2) after the system boot up and PAL TV display properly . then  enable VCLK output (set VIDCTL to 0x2001)

                   3) enable LCD_OE by setting LCDOUT to 0x03

                  4) enable horizontal/vertical sync output by setting SYNCCTL to 0x4003.

                  5) set digital output mode to PRGB by setting VMOD to 0x2043

                 6) set DCLKCTL to 0x801, set DCLKPTN0 to 0x03

         after setting HSTART/HVALID, VSTART/VVALID register, then I can oberserve that vclk pin output 27M clock, h/v sync pin output sync signal, R3/G3/B3/R4/G4/B4/R5/G5/B5/R6/G6/B6 output data, but seems there are nothing ouput at pin R0/G0/B0/R1/G1/B1/R2/B2/G2. it's stange.......

     and I also doubt about how to set RGB666 or RGB888? after reading vpbe spec, I just found the vmod register can set PRGB output, but PRGB include RGB666 and RGB888, is it right ? how to set RGB666 output exactly? thanks 

by the way, I have set PINMUX0 , set PINMUX0 to 0x0180001f. Since I have set PINMUX0 bit 23 , so the pinmux is set to RGB888 mode, and does this means the digital data output format is RGB888? and which document describe PINMUX0 in details? If enable RGB888 , why does R/G/B/0/1/2 output nothing?

thanks for any comments...

feng said:

Setting the REC656 bit will allow the digital bus to output a bt.656 standard stream, however there are additional settings that would have to be handled to actually have digital output, this is just one specifically for bt.656.

Hi, thompson

     I do a simple test:

                   1) boot up from PAL standard tv mode 

                   2) after the system boot up and PAL TV display properly . then  enable VCLK output (set VIDCTL to 0x2001)

                   3) enable LCD_OE by setting LCDOUT to 0x03

                  4) enable horizontal/vertical sync output by setting SYNCCTL to 0x4003.

                  5) set digital output mode to PRGB by setting VMOD to 0x2043

                 6) set DCLKCTL to 0x801, set DCLKPTN0 to 0x03

         after setting HSTART/HVALID, VSTART/VVALID register, then I can oberserve that vclk pin output 27M clock, h/v sync pin output sync signal, R2/G2/B2/R3/G3/B3/R4/G4/B4/R5/G5/B5/R6/G6/B6 output data, but seems there are nothing ouput at pin R0/G0/B0/R1/G1/B1. it's stange.......

     and I also doubt about how to set RGB666 or RGB888? after reading vpbe spec, I just found the vmod register can set PRGB output, but PRGB include RGB666 and RGB888, is it right ? how to set RGB666 output exactly? thanks 

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