TCI6638K2K: a quetion between FPGA and C6638 with AIF modual

Current progress: use DSP as master equipment, FPGA as slave device, use link1 with 8x speed, and serdes line rate is 4.9152G,
use gerneric packet mode with cpri protocol.
(ti example path C:\ti\pdk_keystone2_3_01_03_06\packages\ti\drv\aif2\test\generic\generic.c
changed intLoopback to 0 as external loopback
changed line rate to 8x to fit with FPGA serdes line rate)

It is workable from the DSP send to FPGA data, FPGA use serdes loopback directly data back to the DSP,and data can be verified successful from the DSP,
DSP RM state machine shows synchronization success (RM_LK_STS0 [1] 0x01f50814 = 00000001)

    
  Problem:
1,  If the FPGA canceled serdes loopback, when received dsp data, it replaced them and do their own data encoding ,send back to dsp,
     DSP RM state machine shows synchronization failure (RM_LK_STS0 [1] 0x01f50814 = 00000308)
     But the FPGA cpri recevier state machine shows synchronization success (status code: 6)



I have tried to change RmLink sync Threshold( losDetThreshold UnsyncThreshold FrameUnsyncThreshold ) to max value 65535,
and set bEnableLcvControl ,bEnableLcvUnsync to 0, RM_LK_STS0 [1] can be sync ok (0x01f50814 = 00000001),but raw data in rxbuffer is dirty data,
it seems not working.

how to fix it or can you give any debug advice ?

2,how to get the debug trace information in gerneric packet mode? Or must I have change my project into DIO mode if I want to debug?
Is there any other convient debug tool to get debug information with FPGA connection?