DM385: EMAC REFCLK source in RMII mode

Hi Tony,

Tony Tang said:

The 50MHz EMAC_RMREFCLK output from DM385 quality is bad, can't sustain stable communication.

From what I understand you are configuring pin AG1/PINCNTL232  as output in muxmode1 (EMAC_RMREFCLK) and you do not have stable 50MHz signal on that pin, is that correct? Can you provide more details what do you mean under "quality is bad"? You can check EMAC_RMREFCLK timing requirements in DM38x datasheet, section 8.6.2.2 EMAC RMII Electrical Data/Timing - check RMII Transmit

Tony Tang said:

#1. I did not found a statement in datasheet or TRM to advice customer to use external 50MHz for REFCLK, so is there a way to tune it to meet the RMII requirement of the clock?

Either I do not understand your question here or you do not understand the RMII ref clock scheme. The RMII ref clock scheme is as below:

You can supply 50MHz RMII clock to DM385 CPSW module by:

1. internal 50MHz clock supplied by 20MHz OSC0 and SATA SerDes.

20MHz OSC0 -> SATA SerDes -> 50MHz rmrefclk -> CPSW RMII

2. external 50MHz clock supplied by pin AG21 (EMAC_RMREFCLK). In this case AG21 pin act as input.

EMAC_RMREFCLK -> 50MHz rmrefclk -> CPSW RMII

This is controlled by bit RMII_REFCLK_SRC[0] REFCLK_SOURCE

In case 1 (internal), you can also export this 50MHz to AG1 pin, this time the pin is output:

20MH OSC0 -> SATA SerDes -> 50MHz rmrefclk -> pin AG1

What do you want to tune exactly?

Tony Tang said:

#2. Is there clock quality relate to system CLKIN quality or the PLL?

rmrefclk quality might be impacted by 20MHz OSC0 clock quality and/or DPLL_SATA_SERDES

Pavel,

I mean whether the jitter of EMAC_RMREFCLK -> 50MHz  output from AG21 meet RMII reference clock specification. Because customer use internal source output 50MHz clock to PHY, the Ethernet communication is not stable, replace with a external oscillator 50MHz connect to EMAC_RMREFCLK, then stable.

And customer measured the EMAC_RMREFCLK output from AG21, the jitter is very high.

I saw a Note in OMAP-L138 TRM as below, it state the output clock can't meet RMII clock specification, so I ask whether DM385 has same limitation? If No, Is there customer use ARG21 output 50MHz for RMII in MPed product?

Tony Tang said:

I mean whether the jitter of EMAC_RMREFCLK -> 50MHz  output from AG21 meet RMII reference clock specification. Because customer use internal source output 50MHz clock to PHY, the Ethernet communication is not stable, replace with a external oscillator 50MHz connect to EMAC_RMREFCLK, then stable.

And customer measured the EMAC_RMREFCLK output from AG21, the jitter is very high.

I saw a Note in OMAP-L138 TRM as below, it state the output clock can't meet RMII clock specification,

We do not have this note in DM38x documentation, so I suspect (but not tested) that here it should meet the RMII spec.

We also have silicon errata for the same in AM335x documentation (Advisory 1.0.16), and the problem there RMII ref clock is sourced from high jitter PLL. while in DM38x we source that clock from low jitter DPLLLJ SATA SerDes PLL. See the below e2e threads for more info:

We have also similar silicon errata for AM57x and DRA7x, but I can not find such errata for DM38x.

Regarding the high jitter, you should check OSC0 20MHz clock requirements are met and also SATA SerDes PLL requirements.

Regards,
Pavel

Pavel,

But in the TRM RMII interface connections figure, the RMREFCLK is only input from PHY.  I suppose the figure comes from design document, I am not sure whether designer know the limitation, but forgot to add it into notes.