This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DM6446 Video process sub syetem

hi,
   I am using DM6446 and debugging Video process sub system.

   CCD module of VPFE (video processing front end ) gets video data from
 
   adv7189 decoder.
 
   I want to know if the data that has been processed  by VPFE must be
 
   stored   into  external SDRAM.
  
   Can I store/read directly some data that has been processed by VPFE

   into on-chip

   RAM of DM6446 ??
 
   How ??

   Thanks!!

  • wang shu said:

    Can I store/read directly some data that has been processed by VPFE

       into on-chip

       RAM of DM6446 ??
     
       How ??

    This would depend somewhat on the software stack you are using on the DM6446, for example if you are running Linux you could modify a video loopback example to save a frame or frames to a file so you could examine them later.

    If you are using some other RTOS than there may be alternative debugging methods to view the frame buffers such as through JTAG.

  • Thanks.

    I  use   CCS  to debug  DM6446.

    What is the function of Shanred buffer logic (SBL) of  DM6446? 

    How to use SBL ?

     

  • Thanks.

    I  use   CCS  to debug  DM6446.

    What is the function of Shanred buffer logic (SBL) of  DM6446? 

    How to use SBL ?

  • wang shu said:
    What is the function of Shanred buffer logic (SBL) of  DM6446?

    The shared buffer logic (SBL) described in section 4.4 of SPRUE38e is leveraged by the VPFE itself to write into memory efficiently, it is essentially just the interface between the VPFE and the rest of the system.

    wang shu said:
    How to use SBL ?

    The SBL is not leveraged directly by a user, it is a sub system of the VPSS that is managed indirectly by how you configure the VPFE itself, that is, you configure the VPFE to capture data and the VPFE manages the SBL to write that data into memory. The SBL has some minimal control over internal bus priority as well as status information that can be read from the registers described in chapter 7 of SPRUE38e.

  • Thanks .

    I  want to store  some  video data into  SDRAM.

    Then ,   DSP cpu can read  data  from  SDRAM.

    But,  before    DSP  cpu  read  data  ,   How  can  I  tell   DSP  cpu   that   video  data  has been  stored   into   SDRAM.